Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure cryptographic implementation must detect/correct such a malicious attacks. Error detection /correction (EDC) is an effective way to mitigate such fault attacks in cryptographic hardware. To this end, we analayse the area, delay, and power overhead for designing of S-box which is one of the main complex blocks in the Advanced Encryption Standard(AES), with error detection and correction capability. We use multiple Parity Predictions (PPs), based on various error correcting codes, to detect and correct errors. Different coding techniques are presented, which include simple parity prediction, split parity codes, Hamming, Hsiao, and LDPC codes. The S-box, GF(P), and PP circuits are synthesized from the specifications and the decoding and correction circuits are combined to form the complete designs. The analysis shows a comparison of the different approaches characterized by their error detection capability.