Excessive current density within the interconnect is a major concern for IC designers, which if not effectively mitigated leads to electromigration and electrical overstress. This is increasingly a problem in modern ICs due to smaller feature sizes and higher currents associated with lower supply voltages. Detailed analysis of all interconnect nets is both time-consuming and cannot be done until physical design is complete, when it is too late for easy fixes. To address these problems, we introduce (I) a powerful terminal current value model and (II) an efficient methodology to determine the worst-case bounds on branch currents of the interconnect. This early-stage calculation enables nets to be separated into critical and non-critical sets; only the set of critical nets, which is typically considerably smaller, requires subsequent special consideration during routing and layout verification due to current density design limits. The presented algorithms are fast enough to run on every net, and work with unknown net topology, leading to several practical uses, such as (I) the pre-layout identification of nets that are potentially troublesome and may need sizing, (II) as filter to avoid time-consuming detailed current-density analysis of net layouts, and (III) to evaluate the effect of temperature and process changes on the number and distribution of current-density-critical nets.