Lateral ESD diodes were fabricated, characterized and modeled using Foundry standard 65nm CMOS technology. BSIM4-based lateral diode model was presented for the first time. With the re-use of the MOS transistor model, a physically based scalable lateral diode model was developed. The accuracy of the developed model was validated with RF characterization over geometrical scaling trend. The model was further used for LNA RF performance and ESD CDM protection co-designed. A good match in the RF performance was achieved and the experimental result showed that ESD CDM level with +/-500V could be passed.