As the IC fabrication technology gets into the nanometer era, antenna effect plays an important role in determining the yield and reliability of VLSI circuits. This work proposes a discharge-path-based antenna effect detection method. Based on the proposed detection method, two novel jumper insertion and layer assignment algorithms are presented for fixing antenna violations. In addition, via timing impact is considered in delay calculation, and wire sizing technique is applied for compensating clock skew. Give an X-architecture clock tree with n sinks, layer configuration, and the upper bound of antenna effect, the proposed PADJILA algorithm runs in O(n^2) to achieve antenna violation free. Experimental results on benchmarks show that PADJILA can respectively decrease the numbers of the inserted jumpers and total vias by 48.21% and 20.36% compared with other previous antenna fixing works.