Tuesday March 15, 2011
Sessions 1D, 2D, and 3D
Chair & Moderator: Anand Iyre, Advanced Micro Devices (AMD)
Session 1D, Tuesday March 15, 2011
1. Sandip Ray, University of Texas at Austin email@example.com
2. Jay Bhadra, Freescale Semiconductor Inc. Jayanta.firstname.lastname@example.org
Flash and other non-volatile memories are pervasive in embedded and low-power systems. They serve as the persistent storage in iPods, cellular telephones, medical instruments, automobiles, and many other devices in current everyday use. Memories take up more than 50% of a modern SoC design, both in real estate and transistor count. Furthermore, modern memory implementations are complex artifacts with subtle pipelining, area compression, and power optimization features. Consequently, memory verification is a critical part of the industrial verification tool flow. Memory verification has traditionally used switch-level model of transistors. Unfortunately, switch-level abstractions cannot handle the specialized transistors (e.g., floating-gate and split-gate devices) used in non-volatile memories. Recently, new methods have been devised for flash verification, based on a different model of transistor networks called behavioral abstractions. The newer method has been successfully used for verification of industrial designs containing both floating-gate and split-gate flash implementations. This tutorial will provide a broad overview of formal functional verification of non-volatile memories. We will discuss the traditional approaches, their inadequacies, and how they are overcome in the newer approach. No background is assumed on flash memory design. A key focus of the tutorial is to make the student understand what is necessary to develop a verification solution in a new domain, how to make such a solution scale to industrial problems, and how to integrate the solution with the industrial validation tool flow. All these issues will be illustrated with the flash verification solutions. Finally, we will discuss the potential for the same techniques in the verification of other analog circuits, including PLL, ADC, and DAC.
Session 2D, Tuesday March 15, 2011
1. Riko Radojcic, Qualcomm - “TechTuning : DFM Methodology for Stress Management for 3D TSV Products”
2. Kamal Karimanal, Global Foundries - "Thermo-Mechanical Modeling Techniques for the Estimation of Multi Scale Stresses in 3D IC Packages"
3. Valeriy Sukharev, Mentor Graphics – “Stress Assessment for 3D IC performance: Full chip analysis”
4. Xiaopeng Xu, Synopsys - “TCAD Simulation for Stress Management in 3D IC”
5. Ehrenfried Zschech, Fraunhofer Institute for Non-Destructive Testing IZFP - “Multi-scale materials characterization - Input for stress simulation and model validation"
Management of mechanical stresses is one the key enablers for the successful implementation of 3D integrated circuits using Through Silicon Vias (TSVs). Copper-filled TSV’s and wafers thinned to a few tens of microns modify the stress profiles in the silicon, and may exacerbate the stresses introduced by tier-to-tier bonding and chip-package interactions. These stresses have the potential to modify device characteristics, affecting functional and parametric yield and reliability. This Tutorial will describe a Stress Management Flow intended to support a DFM-like solution that would enable design entities to quantitatively model stress implications on their designs. The proposed flow is a blend of traditional FEA based tools used at package level, specialized FEA tools used to model the effects of mechanical stress on device performance, and a compact model-based “stress hot spot” checker. The established tables of the required material properties, measurement techniques and corresponding simulation use-models will be shared with the participants.
Session 3D, Tuesday March 15, 2011
1. Bhanu Kapoor, Mimasic
2. Amit Kumar, CSR plc
3. Prapanna Tiwari, Synopsys
Power management is important not only for improving battery life of products targeted to wireless, automotive, and consumer electronics markets but also for optimizing meantime between charging and system costs for battery operated devices. In addition, it plays an important role in avoiding high failure rates in devices as well as in reducing cooling costs for products that require high performance. In this tutorial, we will focus on the power management architecture of a global positioning system (GPS) chip targeted for mobile segment that includes a power controller, a power switch matrix, two switched power domains, and some always‐on blocks. Power techniques used on the chip include clock gating, voltage scaling, and power gating. We focus on the verification challenges faced in designing the GPS chip including RTL modeling of power switches, isolation, and level‐shifting cells, simulation of voltage ramps, and generation of appropriate control signals to put the device into various power states. The power management verification strategy was put in place with following goals in mind:
• Ensuring the intent of power‐aware design is implemented per its architecture definition
• Correct sequencing of control signals during the switching and scaling of power supplies
• Correct input and output functionality of each power domain during the power cycles
• Coverage of all power states and all legal transitions between these power states
Some of the specific verification issues encountered and to be discussed here include the following:
• Boot value could not be latched during power up cycle
• Role of placement of inverter and isolation leading to an active low reset error
• Issues with placement of feed‐through buffers leading to functional errors
• Issues with voltages on level‐shifters corrupting signals across domains
• Delay dependent issue with isolation resulting from voltage ramp times