In advanced technology nodes, design for manufacturing (DFM) is critical to address throughout the IC design flow. Traditional DFM signoff-based approaches have long turnaround times and are often employed too late in the design process. This talk describes how advanced node design requires starting with the end in mind; it requires in-design DFM to scale diverse design needs from blocks and IP to large SoCs.
About Vinod Kariat
Vinod Kariat is a Cadence Fellow working in the area of custom design. He has been with Cadence since 2001, holding various management and senior technical positions in the areas of digital implementation, electrical analysis, and variation-aware design. Prior to his tenure at Cadence, he was VP of Engineering at CadMOS Design Technology, a startup devoted to the commercialization of static noise analysis techniques, which he co-founded in 1997. With a Ph.D. from Syracuse University, Vinod is also a Senior Member of the IEEE and holds six patents.
The science fiction of yesterday depicted by such characters as Dick Tracey and Captain Kirk of the space ship Enterprise has stretched the minds of researchers, developers and industry into futuristic programs that span over a range of activities from multifunctional nanoparticle-based smart pills for image sensing and targeted therapy where monitoring agents are encapsulated and activated or monitored with either electromagnetic or light waves, through to new materials conjectured to change the current design practices and product development framework. To gain an economic advantage and in the quest for intelligent integrated systems both industry and academia have invested over trillion dollars in the last decade of research funds towards integration of radically differing technologies. Although many of such programs are in their embryonic phase, they continue to be the catalyst for future generation of products showing new possibilities for a variety of intelligent-based systems such as i-Health Care and i-Aged Care, i-energy management, i-environmental monitoring, i-security etc. The revolutionary marriage of nanoelectronics with photon and bio based sciences driven by new materials is becoming the enabler of novel circuits and systems with extraordinary new properties relevant to every sector of the economy. The presentation will provide an overview of the inevitability of heterogeneous integration using technologies that are either in their infancy or yet to be developed and will focus on new developments in a number of technology domains conjectured to challenge the perspective and the mind-set that researchers and industry currently may have.
About Kamran Eshraghian
Kamran Eshraghian received his PhD, MEngSc, and BTech, degrees from the University of Adelaide, South Australia. In 2004 he was awarded the Dr.-Ing e.h., from the University of Ulm, Germany, for his research into integration of nanoelectronics with that of light wave technology. He is best known in international arena as being one of the fathers of CMOS VLSI (Very Large Scale Integration) having influenced two generations of researchers in both academia and industry. In 1979, he joined the Department of Electrical and Electronic Engineering at the University of Adelaide, South Australia, after spending some ten years with Philips Research, both in Australia and Europe. In 1994, he was invited to take up the Foundation Chair of Computer, Electronics and Communications Engineering in Western Australia, and became Head of School of Engineering and Mathematics and Distinguished University Professor and subsequently became the Director of Electron Science Research Institute. In 2004 he founded ELabs as part of his vision for horizontal integration of nanoelectronics with those of bio and photon-based technologies, thus creating a new design domain for System on System (SoS) integration. Currently he is the president of Innovation Labs and also serves as the Chairman of the Board of Directors of two Hi Tech companies. In 2007 he was the holder of inaugural Ferrero Family Chair in Electrical Engineering at University of California Merced and visiting Professor of Engineering prior to his move in 2009 to Chungbuk National University, Korea, as Distinguished Professor, World Class University (WCU) program. He has co-authored six textbook and has lectured widely in very large scale integrated and multitechnology systems. He has founded six High Technology companies, providing intimate link between University research and industry. He is the Fellow and Life Member of the Institution of Engineers Aust.
'When Moore first described his 'law' the rate-limiting factors to cramming more transistors onto a chip were defect density and circuit design. But for the last 30 years it has been lithography that has been the key pacing item. Now the awful cost of pushing lithography to finer features leads us to look at alternatives. These mostly take some form of exploiting the third dimension so we can stack transistors as well as the wiring. The techniques vary from simply putting one thinned chip on top of another to monolithically fabricating a circuit in which transistors as well as the interconnects are formed at each level.
About R. Fabian W.Pease
Pease served as a radar officer in the Royal Air Force from 1955 to 1957, and received his B.A., M.A., and Ph.D. degrees from Cambridge University in 1960, 1962, and 1964, respectively. His Ph.D. thesis was on High Resolution Scanning Electron Microscopy. After graduating, he was an Assistant Professor of Electrical Engineering at UC Berkeley where he continued his microscopy research. In 1967, Dr. Pease joined Bell Laboratories, where he first worked on digital television and later led a group that developed the processes for electron beam lithographic mask manufacture, and demonstrated a pioneering LSI circuit built with electron beam lithography. Since 1978 he has been a Professor of Electrical Engineering at Stanford University. His group’s research includes micro- and nano-fabrication and their application to electronic and magnetic devices and structures. This work has included the original demonstration of lithography with the scanning tunneling microscope, exploring the limits of resolution of deep ultraviolet lithography, the invention of the micro-channel heat sink and non-conventional electron beam technology for semiconductor manufacturing. On sabbatical in 1993 and 1994, Dr. Pease researched the synthesis of DNA microarrays at Affymetrix Corporation. From 1996 to 1998, he was assigned to the Defense Advanced Research Projects Agency, where he initiated programs in Advanced Microelectronics and in Molecular-Level Printing. He has served as a consultant to IBM, Xerox, Etec Systems, and Lawrence Livermore Labs and is several Technical Advisory Boards. Dr. Pease was appointed the William E. Ayer Professor of Electrical Engineering in March 2001. He is a Fellow of the IEEE, and a member of the National Academy of Engineering. With his student, David Tuckerman, he received the first IEEE Paul Rappaport Award. He was also the recipient of the IEEE Cledo Brunetti Award in 2001, for advancing high resolution patterning technologies, high performance thermal management, and scanning electron microscopy for microelectronics. Other honors include the Richard P. Feynman Prize for Microfabrication, which he shared with student, Tom Newman, for writing a page of text in a 6 micron square with 25nm linewidths; and a Title A Fellowship from Trinity College, Cambridge.
Complex chips with multiple processors are being designed today to achieve aggressive performance and low power targets. However, multi processor chips create a huge quality challenge around HW and SW co-design. How to develop, debug and verify HW and SW functionality in a multi processor design? How to manage memory coherency and integrate multiple, dependent SW stacks? In the last few years, virtual prototypes have emerged as a way to run system level tests and perform hardware/software co-simulation and co-debugging before silicon or hardware prototypes are available. This presentation will present virtual prototyping and its merits for quality hardware/software design.
About SEshel Haritan
Eshel Haritan joined Synopsys as vice president of engineering for the System Level Solutions group in March 2010 as part of the CoWare acquisition. He is managing the Synopsys system level products R&D including the recently acquired products from CoWare and VaST. Before joining Synopsys Haritan served 7 years as vice president of engineering for CoWare Inc. and prior to that he managed for 8 years the Cadence System Level Design R&D. Prior to Cadence Haritan served in the Freescale Israel CAD group.
With consumer electronics driving the IC industry, opportunity windows are shorter than ever, while the scale and complexity of IC design continues unabated following Moore’s Law. One of the key areas of concern is the rising cost of design creation, and there are many Doomsday predictions of design costs becoming unaffordable. While most of the industry buzz is around system level design improvements, the pressure keeps growing for teams working closer to silicon manufacturing. This talk will focus on the challenges of physical design, and EDA advances required to shorten design cycles. For example, reuse of physical IP is a necessity to meet the future challenges of IC design, but integration of IP from many sources is a huge problem because it can introduce “fragility” into the manufacturing process, resulting in unpredictable yield and performance. A viable solution requires improvements in technical implementations as well as operational agreements across multiple supply chain members. Another example is how to reduce the number of iterations required for design closure by bringing more accurate signoff models to bear earlier in the design flow.
About Juan C. Rey
Juan C. Rey is the Senior Engineering Director for the Design to Silicon Division at Mentor Graphics Corporation; his group is responsible for the architecture, design and development of the Calibre line of products used for integrated circuits physical verification and tape out tasks such as design rule checking, layout vs. schematic verification, capacitance, resistance and inductance extraction, resolution enhancement, mask data preparation and design for manufacturing. Juan has 25 years of software development experience ranging from research activities at Stanford University (EE department), to development and management (at Technology Modeling Associates, Cadence and Mentor Graphics) of process and device modeling software. His most recent 15 years have been in Electronics Design Automation and semiconductor processing modeling.
3D integrated circuits are starting to make their way into the market place. The new technology offers great rewards in terms of power savings, density, and performance, but also carries new design and manufacturing challenges. The speaker will review various 3D integration technologies and discuss the current state of the art. He will also cover the impact on design and test.
About Robert Patti
Bob Patti is the Chief Technology Officer of Tezzaron Semiconductor Corporation, a leading force in 3D-IC technology. Tezzaron built its first working 3D-ICs in 2004 and now uses wafer-level stacking processes to create ultra high-density 3D memory products and other semiconductor sub-components. Before Tezzaron, Mr. Patti founded an R&D company specializing in high-performance systems and ASICs; he participated in the design of more than 100 chips over the course of 12 years. Mr. Patti received the SEMI Award for North America in 2009, served as Vice-Chairman of JEDEC's DDRIII / Future Memories Task Group, and holds 15 US patents, numerous foreign patents, and many more pending patent applications in deep sub-micron semiconductor chip technologies. He earned Bachelor of Science degrees in both physics and electrical engineering from Rose-Hulman Institute of Technology.
While Home automation technologies have been around for many years, they have so far seen adoption only in either very expensive homes or with do-it-yourself hobbyists. The rollout of the smart-grid infrastructure has generated a renewed interest in the dream of mass-adoption of smart-home capabilities with smart-appliances, networked lighitng controls, and smart HVAC systems. In this talk, we will explore the changes happening in the market place to bring about these smart-connected devices and systems in the home and connecting these to the smart-grid infrastructure and services. We will discuss the enablers for this vision to become a reality in the near-future, as well as challenges that need to be overcome.
About Manas Saksena
Dr. Manas Saksena is leading Marvell's efforts to enable smart-grid applications by offering smart-connectivity solutions for devices such as meters, thermostats, appliances, load-controllers, outlets, and lighting controllers. Dr. Saksena received his B. Tech degree in 1988 from Indian Institute of Technology, Kanpur, and his Ph.D from University of Maryland, College Park in 1994. He spent six years as an academic researcher focusing on real-time systems, and published a number of research papers. He joined TimeSys Corporation in 2000, and was the CTO of TimeSys Corporation. At TimeSys, he was responsible for technology and product development on Embedded Linux products and services. He joined Marvell Semiconductor's in 2006 as an Embedded Linux and Open-Source expert before morphing into his current role.