This paper presents a new design methodology for analog circuit synthesis in submicron technology. This design methodology takes circuit performance specification as input and it terminates at producing layout of the generated circuit for the given specification without any user intervention within few minutes. In conventional equation based circuit sizing technique there is high chance that the optimized design point is at the boundary of the feasible design space and due to process variation the design point may fall outside the feasible design space and resulting poor yield. We use conventional design centering technique to make our design robust against process variation present in submicron technology and assure yield of the generated design. The novelty of this methodology is in formation of the design centering problem as a sequence of Geometric Programming Problem which renders this methodology computationally inexpensive compare to others. We prove the yield improvement through Monte Carlo simulation. Analog designs are sensitive to its layout. Common centroid layout , fingering ,conforming the design dimension to technology grid point these layout related issues are considered in design phase and we produce device dimension with which direct layout is possible.