In recent years, the rise in the number of cores being integrated on a single chip has led to a greater emphasis on scalable communication fabrics that can overcome data transfer bottlenecks. Network-on-Chip (NoC) architectures have been gaining widespread acceptance as communication backbones for multi-core systems, due to their high scalability, predictability, and performance. However, NoCs are also power hungry, and synthesizing a NoC fabric for a particular application requires solving a multitude of non-trivial design problems. Due to the large design space associated with various possible NoC configurations and design constraints, it is critical to automate the exploration process and arrive at a customized NoC that meets performance goals, while minimizing power and peak temperature. In this paper, we present a novel application specific NoC synthesis framework (POSEIDON) that combines multiple algorithms and heuristics to efficiently explore the solution space. Our results indicate that the proposed framework provides a reduction of up to 15.7% in power consumption, 21.08% in average latency, 27.05% in total energy, and 42.7% in energy-delay product compared to state-of-the-art approaches, as well as a 4.2% reduction in peak temperature when the framework is customized for thermal-aware synthesis.