Radiation effect and soft error problem in digital circuits are becoming increasingly important as the CMOS technology moves to the nanometer scale. This paper presents a soft error hardened latch circuit suitable for reliable operation. The proposed circuit is aimed to tackle the particle hit effect on the internal nodes of the latch and the external logic, as well as the pulse generator circuit. The hardening method is based on the use of redundancy to protect internal nodes, and also skewed CMOS gates to filter out transients resulting from combinational logic. To further reduce the soft error rate, the proposed circuit uses redundant clocking technique which results in more robustness and less timing overhead. Circuit is designed in 90 nm CMOS technology and simulated with HSPICE. Besides normal mode verification, circuit is tested against particle hit on external logic and internal nodes using current pulse injection method. Simulation results indicate that in addition to lower-power and -delay, the circuit is able to recover from almost any single particle stroke on internal storage and clock nodes, and can tolerate input transients up to 120ps of durations.