Stringent design rules and RET (resolution enhancement technique) measures prevent occurrence of interconnect opens and shorts. However, success of this strategy depends on completeness of physical design rules. In deep sub-wavelength lithography, all physical design rules or their context sensitivity to reticle position may not be fully understood a priori. As a result defects may arise in silicon due to line edge placement errors (EPE). Such EPE often result in soft-faults, characterized by high coupling capacitance induced by interconnect near-bridges or high resistance interconnect induced by pinches. In this paper, our goal is to identify missing design rules by response analysis of defective chips to test stimulus. To this end, we provide a general solution to the problem. Experimental results report the number of manufacturing suspect tiles to be included in the missing design rules set for a reference case. Thus we provide a mechanism to automate missing physical design rule discovery through test response analysis of defective silicon.