The degradation of MOSFET device performance in time (aging), caused by hot-carrier injection (HCI) and negative/positive bias-temperature instability (N/PBTI), is increasingly more responsible for IC reliability failure in advanced process technology nodes. Device scaling, that has allowed increased performance of CMOS circuits, has also resulted in a magnification of such reliability issues. At the same time, device and circuit designers face increasingly stronger requirements to provide realistic estimates of product reliability as a function of circuit operation conditions. Accurate aging modeling and fast yet trustable reliability signoff have thus become mandatory in process development and circuit design. This paper presents an accurate and scalable compact device aging model that takes into account accurately the HCI and BTI mechanisms and is silicon proven for various processes down to 32/28nm. The model formulation on bias, geometry and temperature and, in particular, a unique methodology for modeling the AC partial-recovery effect of BTI, is analyzed in detail. The model has been embedded in an efficient MOSRA circuit simulation flow and has been used successfully for numerous tapeouts and silicon debugging for 45nm and below.