Bias Temperature Instability (BTI) causes significant threshold voltage shift in MOS transistors using Hafnium oxide (HfO2) High- k dielectric material. Negative BTI and Positive BTI are two types of BTI effects observed in p- channel and n- channel devices. BTI affects the stability and reliability of conventional six transistor (6T) SRAM design in Nano-Scale CMOS technology. Eight transistor (8T) and Ten transistor (10T) SRAM cell designs are known for their ability to operate at lower supply voltages to reduce power consumption. In this paper, we present a comparative analysis of different SRAM cell designs in terms of their reliability against BTI effects. For a fair comparison, voltage scaling is applied to the 8T and 10T cells to a level where they show same Static Noise Margin (SNM) as that of the 6T cell at nominal supply voltage. In a predictive 32nm CMOS technology, the supply voltage of 8T and 10T cells is reduced to 0.418 V which is 54% lower than the nominal supply voltage (0.9 V), which the 6T cell is biased at. Due to lower supply voltage in 8T and 10T SRAM designs, the impact of BTI is lower and reliability is far better than the 6T SRAM design, while achieving signifi-cant leakage power reduction. Based on the simulation results, we recommend designing SRAM arrays using 8T SRAM cell or 10T SRAM cell in future nano-scale CMOS where BTI effect is a re-liability barrier for SRAM design.