During the billion transistor era, 3D stacking offers an attractive solution for the difficulties resulting from large-scale design complexities. Moreover, 3D stacking can benefit performance, power, bandwidth, footprint, and heterogeneous technology mixing. However, before adopting the 3D design strategy, this study seeks to understand how much cost is required to trade these benefits. This paper proposes a 3D IC cost evaluation framework based on fast tier number estimation. Using a reformulated Rent's rule, this study efficiently determines the number k of tiers to minimize the through-silicon via count and then automatically partitions a gate-level netlist into k tiers to minimize the total cost. This study conducted experiments on eight industrial test cases to show cost efficiency and effectiveness. Moreover, results prove that the reformulated Rent’s rule indicates a strong correlation between the tier number and through-silicon via usage.