Analysis and tackling of NBTI wearout effects are important design objectives in microprocessor designs. Application induced stress, combined with circuit-architectural design styles creates widely diverging wearout characteristics in a processor datapath. Moreover, in a typical case in desktop computing, different applications can interleave. This interleaving can cause destructive interference in stress patterns leading to substantially worse aging effect than an isolated application. We investigate NBTI wearout degradation in a register file using a comprehensive circuit-architectural analysis of SRAM cells, and show that recently proposed periodic bit inversion is unable to cope with interleaving application induced stress. We propose two novel micro-architecture techniques to mitigate this limitation. Our techniques reduce the Static Noise Margin (SNM) by 2.2X, while improving the degradation uncertainty by 14X over current state-of-the-art techniques. Our overhead analysis shows that both area and power overheads of our proposed technique can be minimal in the context of the reliability improvement it provides.