Standard cells are basic building blocks, crucial for digital designs. Manufacturability improvements in standard cells have huge leverage, returning big benefits in yield and performance to all designs which may use them. Most of the benefits can be obtained by making changes to relatively few transistors in the cell, early in the design cycle. This paper presents a methodology to make standard cells more robust to manufacturing variations using DFM guidelines and knowledge of circuit performance sensitivity. Sensitivity analysis to variation parameters is performed to determine the critical cells and the critical transistors within those cells. Layout changes for DFM guidelines are performed selectively on the sensitive transistors within the cells. Results using the proposed methodology shows that there are as much as ~2X improvement in DFM-violation score in a 45nm technology library. The proposed methodology also reduces the total-net capacitance in the cells by as much as ~2%. These improvements are obtained without penalizing the cell area and cell pin-outs.