Low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) have emerged as a promising technology for applications such as in low-cost sensor networks. In this paper, we propose a LTPS TFT device optimization methodology based on scaling of silicon body (Tsi) and buried oxide thickness (Tbox). The proposed approach is applicable for both digital and analog circuits. Results show that, using the optimized device we can achieve 133X improvement in oscillation frequency of a 3-stage ring oscillator (RO) and 31% improvement in operational amplifier (OPAMP) gain (Tsi =10nm and Tbox =10nm) compared to the traditional device structures. We believe that proper optimization of TFT device geometry parameters is necessary to realize low power, high performance, and low-cost LTPTS TFT digital & analog/RF circuits.