Modern microprocessor caches are often regarded as cool chip components that dissipate power uniformly. This research demonstrates that this uniformity is a misconception. Memory cell peripherals dissipates considerably higher power than the actual memory cell and this can result in up to 30oC of temperature difference between the warmest and the coolest cache part. To be effective and accurate, cache temperature and power modeling and management must take this effect into account. We focus on the surrounding logic of the memory cell and apply two novel techniques, peripheral bit swapping (PBS) and peripheral monitor and shutdown (PMSD), to reduce the thermal variation and reduce the corresponding steady-state temperature and leakage power of the cache. Overall, our techniques, on average, decrease temperature by 8oC for the L1 Data Cache and 5oC for the shared L2 cache and reduce their thermal gradient by more than 75%, on average, and across SPEC2K benchmarks.