The performance of SRAM varies depending on operating environment. In this paper, we especially focus on a bit error rate (BER) when considering temperature fluctuation. In the SRAM, a read margin decreases at high temperature whereas the write margin degrades at low temperature. The performance of SRAM is generally determined by the read operation margin because a half-select issue must be considered even in the write operation. As a metric of the SRAM’s performance, we adopt a static noise margin (SNM), with which we introduce three methods to estimate the BER considering temperature fluctuation. Method 1 calculates SNM many times with Monte Carlo simulation and BER is defined the number of cell which has no margin. Method 2 uses an assumption SNM follows normal distribution and BER is defined a probability that SNM is less than zero. Method 3 is same as method 2 except SNM’s define. Method 3 is considered that SNM is determined only one square, and is not smaller one of two squares. The BER estimations are compared with a test chip result implemented in a 65-nm CMOS technology. In method 1, it is difficult to estimate the Vmin at large memory capacity because of its long simulation time. Compared with the measured Vmin at 128-Kb memory capacity, those of method 2 and 3 are lower by 11.10 % and 4.09 %, respectively. And Vmin is both 0.04 V at 128-Kb capacity when temperature fluctuates from 25°C to 100°C.