Multi-fin bulk silicon FinFET-based design issues and implications using 3D numerical simulation are presented for the first time. In order to gain sufficient drive current of each transistor, multi-fin layout is inevitable due to limited aspect ratio or fin height. However, how the multi-fin design impacts the circuit performance needs to be taken into account. Because of non-planar nature of the fin, conventional concept of multi-finger design in bulk CMOS technology does not apply. We found an extra leakage path underneath the fin spacing between source and drain. Such impact can be mitigated by additional substrate doping and proper gate-to-substrate isolation. Based on the proposed design window at a tight pitch control, good performance can be achieved while meeting leakage current requirement.