3D-SOC technology has significant performance and power gains over 2D as interconnects can be shortened significantly. To accrue full benefits of reduced interconnect lengths large designs need to be partitioned into several dies.
In this work we propose a hypergraph based multi-objective circuit partitioning scheme for 3D-SOCs that simultaneously reduces the number of inter die connections, which use through silicon vias (TSVs), and reduces additional DFT logic needed for pre-bond test of dies. An Ordered Block hypergraph partitioning scheme is proposed to achieve these objectives. Experimental results on several industrial circuits demonstrate the effectiveness of the proposed approach.