The down scaling of feature sizes and higher process variations in future CMOS nano-technologies are anticipated to introduce higher manufacturing anomalies. On the other hand designs are getting more complicated due to more innovative applications where they need higher numbers of transistors. These phenomena significantly reduce the functional yield. Redundancy has been used for a long time in regular structures such as memory to tolerate defects; however, for typical irregular logic circuits this would be very challenging. In this paper we introduce a theory that justifies the necessity of using redundancy at sub-chip level of granularity to maximize yield/area (number of healthy dies) for future technologies with higher defect rates. In addition, redundancy at finer levels of granularity, aggravates the overheads of interconnect (steering logics, i.e., forks, joins and switches) such as yield, area, and testing overheads. These overheads limit the level of granularity for logic replication. Current yield estimators are generally pessimistic for interconnects because they do not take circuit and logic context into consideration, and/or they assume all defects are killer-defects, i.e., always result in unacceptable circuit behavior. In this paper we propose a CAD tool to compute the functional yield of the configurable and testable steering logics using (i) actual layout geometries, and (ii) factory data related to density and size of opens (missing metal), shorts (extra metal) and open vias. The experimental results show that our theory of redundancy considering the overheads of steering logics can improve the yield/area by 2.8 times for a real highly-defected circuit (OpenSparc T2 core).