For successful adoption of through-silicon-via-based 3D ICs, delay estimation techniques on 3D interconnects for early design stages are required. Through-silicon vias (TSVs) have large RC parasitics and these 3D nets may connect components placed far apart. Thus buffers are inserted to reduce delay of the nets. To make good decisions in early design stages, it is important to have fast and reasonably accurate buffered delay estimations. However, there has been no buffered delay estimation work for 3D ICs that considers proper delay models and TSV RC parasitics. In this work we investigate several analytical delay models for 3D net delay estimation. Then based on analytical formula and our heuristic algorithm, we propose how to estimate the buffered delay for movable TSV cases and fixed TSV cases. The effectiveness of our delay estimation technique is demonstrated with various 3D nets. Compared with the widely-used van Ginneken style buffer insertion based delay estimation, our estimation provides solutions about 100 times faster with almost same or negligibly increased delay.