Monday, March 19, 2012
Chair & Moderator: Syed M. Alam - Everspin Technologies, Inc.Co-Chair: Volkan Kursun - HKUST
Brian Leibowitz, Rambus Inc.
Exponential increases in single-die compute throughput have outpaced off-chip interconnect density scaling, requiring that memory interface bandwidth increases be satisfied with dramatic increases in per-pin bandwidth. At the same time, compute platforms from servers to GPUs to mobile SoCs have all run into strict thermal and energy consumption limits. These trends have had a dramatic impact on recent memory interface designs, and have also prompted significant industry investment in dense 3D interconnect technologies such as TSVs in an attempt to alleviate the challenges of high per-pin bandwidth. However, compute platforms have widely differing memory subsystem requirements, and there is no-one-size-fits-all solution. This tutorial will review the key specifications of memory subsystems and evaluate the advantages and limitations of a variety of design techniques such as low swing signaling, resonant clocking, DVFS, and fast power state transitions, as well as those of emerging 3D packaging methods. This will show how different solutions are suited to a variety of applications from servers with hundreds of DRAM devices per CPU to mobile devices with as few as one DRAM device, and with practical workloads where interface utilization and dynamics can greatly impact actual efficiency and performance.
About Brian Leibowitz
Brian Leibowitz received the Bachelor of Science degree in Electrical Engineering as well as the Edwin H. Armstrong Award from Columbia University in 1998. In 2004 he received a Ph.D. in Electrical Engineering and Computer Science from UC Berkeley, where his doctoral research included the developed a fully integrated CMOS imaging receiver for free-space optical communication. His graduate studies at Berkeley were supported by a fellowship from the Fannie and John Hertz Foundation. Since 2004 he has been with Rambus, Inc. in Sunnyvale, CA, where he has worked on equalization and mixed-signal circuit design for a variety of high-speed and low power serial links and memory interfaces.
Puneet Gupta, University of California, Los Angeles
Scaling of physical dimensions faster than the optical wavelengths or equipment tolerances used in the manufacturing line has led to increased process variability and low yields which make design process expensive and unpredictable. "Equivalent scaling" improvements - perhaps as much as one full technology generation, can come from looking "up" to circuit design. With few examples from the lithographic patterning, and mask flows, I will illustrate how design information can be leveraged practically to radically reduce pessimism inherent in semiconductor manufacturing as well as guide process research and development. There is a dire need for quick, quantitative and early evaluation of technologies in design context, given the vast spectrum of candidate fabrication technologies available for future semiconductor manufacturing. I will describe early attempts at such a framework to co-optimize design rules, layouts and patterning technologies.
About Puneet Gupta
Puneet Gupta (http://nanocad.ee.ucla.edu) is currently a faculty member of the Electrical Engineering Department at UCLA. He received the B.Tech degree in Electrical Engineering from Indian Institute of Technology, Delhi in 2000 and Ph.D. in 2007 from University of California, San Diego. He co-founded Blaze DFM Inc. (acquired by Tela Inc.) in 2004 and served as its product architect till 2007. He has authored over 70 papers, ten U.S. patents, and a book chapter. He is a recipient of NSF CAREER award, ACM/SIGDA Outstanding New Faculty Award, European Design Automation Association Outstanding Dissertation Award and IBM Ph.D. fellowship. Dr. Puneet Gupta has given tutorial talks at DAC, ICCAD, Intl. VLSI Design Conference and SPIE Advanced Lithography Symposium. He has served on the Technical Program Committee of DAC, ICCAD, ASPDAC, ISQED, ICCD, SLIP and VLSI Design. He served as the Program Chair of IEEE DFM&Y Workshop 2009, 2010. Dr. Gupta's research has focused on building high-value bridges across application-architecture-implementation-fabrication interfaces for lowered cost and power, increased yield and improved predictability of integrated circuits and systems.
Farhang Yazdani, BroadPak Corporation
As the semiconductor industry migrates toward extreme monolithic foundry level 3D heterogeneous structures for mixed-signal components and systems, 3D silicon/glass interposer and through silicon via (TSV) technology will play a significant role in next generation 3D packaging solutions. It is ubiquitous that 3D integration technologies are well suited to realize high density and high performance heterogeneous systems. 3D integration technologies rely on TSV technology, wafer thinning/handling technology and micro-bump technology. This tutorial presents the Process, Application, Requirement and Infrastructure of Silicon Interposer and Through Silicon Via Technologies to empower successful 3D integration.
About Farhang Yazdani
Farhang Yazdani is the President and Chief Technical Officer of BroadPak Corporation. With over 17 years of experience in semiconductor packaging industry, he is widely regarded as an expert on 3D packaging technologies. Previously, he served in various management, technical and advisory positions with leading semiconductor companies worldwide. He has numerous publications and US patents issued and pending in the area of Packaging and Assembly, serves on various technical committees and is a frequent reviewer for IEEE Journal of Advanced Packaging. He has undergraduate and graduate degrees in Chemical Engineering and Mechanical Engineering from the University of Washington, Seattle. He is a member of AICHE, ASME, IEEE, IMAPS, SPE and the Society of Rheology.
Rafael Rios, Intel
The exponential decrease of feature sizes has been relentless and in line with Moore's law for over 40 years. The pursue of ever smaller building blocks is not just a fad driven by a self fulfilling prophecy. Rather, the scaling down of semiconductor components has been the driving force behind the computer revolution. In this talk we will explore the innovations that lead to extending Moore's law into nano-scale feature sizes, including advances in device design, computational lithography, and materials engineering. We will also explore current research work looking into extending Moore’s law into the future.
About Rafael Rios
Rafael Rios received the Ph.D. degree in Electrical Engineer from Drexel University, Philadelphia, PA, in 1990. From 1986 to 1992, he was with the David Sarnoff Research Center (former RCA Labs), working in the fabrication of rad-hard devices. From 1992 to 1996, he joined the semiconductor group of Digital Equipment Corporation, where he was involved in device simulation in support of the Alpha chip development. He is currently a senior researcher in the Manufacturing Group of Intel Corporation, working in the modeling, fabrication, and characterization of devices for future technology generations. Dr. Rios has over 40 publications in the device research area and holds multiple patents.
Hsien-Hsin S. Lee, Georgia Institute of Technology
As device scaling faces several fundamental changes due to physical limitations, die-stacked 3D integration is emerged as the frontrunner technology to continue Gordon Moore’s prophecy in the vertical dimension. It enables a true System-on-Chip design style by stacking multiple die, fabricated with either homogeneous or heterogeneous processes, onto the same package using 3-D inter-die vias or through-silicon vias (TSV). This highly anticipated solution not only packs more transistors for a given footprint, it could also offer several potential advantages, e.g., high memory bandwidth, low power consumption, fast interconnect, flexibility in integration, and a much smaller form factor of a system, etc. Nevertheless, to exploit the maximum potential of this novel integration and packaging technology, the logistics of the system design must be reconsidered and re-evaluated to leverage the effective use of 3D vias. In this talk, I will discuss the opportunities, caveats, and challenges of 3-D stacked IC technology from the perspective of a computing system design and present my view of its prospective outlook. I will also discuss the experiences and lessons we learned from the 3D-MAPS many-core chip that we, at Georgia Tech, designed and fabricated to demonstrate certain targeted performance benefits by using 3-D stacked IC technology.
About Hsien-Hsin S. Lee
Dr. Hsien-Hsin S. Lee is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology. He received appropriate education in Taiwan, and his M.S. and Ph.D. degree in Computer Science and Engineering from the University of Michigan, Ann Arbor. His main research interests include computer architecture, energy-efficient computing, cyber security, and the emerging 3-D IC technology. Prior to joining Georgia Tech in 2002, he spent 6 years as a senior processor architect and a researcher at Intel Corporation designing Pentium III processor and performed research for Itanium architecture and one year at Agere Systems as an architecture manager for their StarCore DSP. Dr. Lee’s received the Horace H. Rackham Distinguished Dissertation Award from the University of Michigan, an NSF CAREER Award, an US Department of Energy Early CAREER Award, the Georgia Tech ECE Outstanding Jr. Faculty Award, and an IBM Faculty Award. He had co-authored 4 papers that won the Best Paper Award in MICRO-33, CASES-2004, IBM PAC2, and ANCS-11, one paper selected in IEEE MICRO Top Picks of Computer Architecture Conferences in 2010, and another three nominated for the Best Paper Award including MIT HPEC-07, FPL-07, and ICCAD-09. He holds 4 U.S. patents and is a senior member of both the ACM and the IEEE.
Stephen Pateras, Mentor Graphics
3D IC offers a compelling alternative to traditional scaling for achieving advances in performance, reduced power consumption, cost reduction, and increased functionality in a small package. Unfortunately 3D IC packaging also creates some new challenges for manufacturing test. Wafer sort will need to deliver higher test quality to ensure acceptable final package yields and thus limit the cost impact of stacking bad die in a 3D package. Stacked die also create significant test access problems since the die-level I/O may not be accessible from within the package. Ensuring that all inter-die TSV connections are adequately tested further complicates the overall test problem. This tutorial will review test solutions available to cost-effectively test 3D ICs from wafer sort to packaged assembly.
About Stephen Pateras
Stephen Pateras is product marketing director within Mentor Graphics Silicon Test Solutions group and has responsibility for the company’s ATPG and DFT products. His previous position was VP Marketing at LogicVision where he was instrumental in defining and bringing to market several generations of LogicVision’s semiconductor test products. From 1991 to 1995, Stephen held various engineering lead positions within IBM’s mainframe test group. He received his Ph.D. in Electrical Engineering from McGill University in Montreal, Canada