With feature sizes far below the wavelength of light, variations in fabrication processes are becoming more common and can lead to unpredictable behavior in modern multiprocessor system-on-chip (MPSoC) designs. The design costs associated with margining required to overcome this unpredictability can be prohibitively high. System-level design approaches that are aware of these variations can be crucial for designing energy-efficient systems. We note that by performing voltage island placement appropriately, the two major unintended consequences of variations on the circuit characteristics (altered delay and power dissipation) can be traded-off, in order to minimize overall system energy. To this end, we propose a novel design-time system-level synthesis framework that is cognizant of process variations while mapping cores operating at specific supply voltages to a die and allocating communication routes on a 2D-mesh network-on-chip (NoC) topology for optimal energy-efficiency. Our framework results in 3.4% savings in computation energy and 19% savings in communication energy compared to the best known prior work on NoC-based MPSoC synthesis that considers process variations.