Current technology scaling trends are changing the character of wire delay variability. The distribution of wire delay is asymmetric, with a long positive tail which can be as much as 2X longer than the negative tail. This is due to the geometry of these wires, where the aspect ratio is biased towards tall thin wire cross-sections, as well as manufacturing induced variations particularly from lithography. These trends are important for timing closure, whether done via corner-based or statistical analysis. In this paper, we explore these trends, demonstrate their impact in a modern 32nm CMOS design, and suggest ways in which this trend can be managed and reduced. Particularly, through physical synthesis optimizaiton on industrial designs, we show how these trends/observations can be utilized to produce more reliable designs. As the interconnect scaling lags behind the device scaling, the importance of wire variability will grow further in the future technology nodes.