Clock Tree Synthesis (CTS) mainly consists of two steps: 1) clock tree topology generation and 2) buffering and embedding. Due to the lack of the efficient model of TSVs, most previous CTS of 3D ICs ignore the effect of TSV planning in the first step. In this paper, we study the TSV-aware clock tree topology generation for 3D ICs by solving two major issues that the previous work has neglected: 1) the density distribution of allocated TSVs; 2) the parasitic and coupling effects induced by TSVs in constructing the topology of clock tree. The experimental results show that considering the impact of TSVs on 3D clock network in the topology generation step can meet the manufacture limitations and enable the designers to obtain the tradeoff among power consumption, the total wire length and the total number of TSVs. The experimental results show that TSVs number and power consumption can be reduced by up to 89.6%and 40.16% respectively with little variation of the total wirelength (the sum of total TSV equivalent wirelength and horizontal wire length) compared to the traditional NNG-based method. Besides, the mitigation of TSV-to-TSV coupling effect in 3D clock tree by implementing the proposed 3D CTS method is demonstrated in our experiment.