Transistor aging due to Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) is one of the major reliability issues for VLSI circuits fabricated at nanometer technology nodes. Transistor aging increases the circuit delay over the time and ultimately leads to lifetime reduction of VLSI chips. Accurate aging-aware timing analysis is a key requirement to consider these effects in the design cycle. Our analysis shows that a separate (independent) analysis of different sources of aging leads to significant overestimation of post-aging delay. To overcome the problem of existing methods, we propose a new aging-aware gate delay model that precisely captures the combined effect of different aging sources on delay. Our results obtained from a set of benchmark circuits show that, our proposed gate-delay model estimates the aging-induced ∆delay by 7.8% (translating to 36.0% MTTF) more accurately in comparison to prior techniques. Moreover, we present a flow for integrating the proposed gate delay model with commercial timing analysis tools.