This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The resilient cache can perform voltage/temperature variation adaptive sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM that can change itself dynamically to a reliable bit-enhancing mode and on-chip voltage/temperature monitoring circuit that can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically reconfigure its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. It does not fail with 25% and 30% droop of Vdd. It provides ×91 failure rate improvement with a 35% droop of Vdd compared with the conventional design. The processor simulator shows that the proposed cache running in the bit-enhancing mode results in 2.88% IPC loss on average.