A spread spectrum clock generator (SSCG) for higher modulation rate suitable for display applications is proposed using varactor based delay line and a dejittering PLL. The varactor based delay line utilizes the delay to phase-modulation property to generate an intermediate spread-spectrum clock. This SSCG has been fabricated in a 0.18µm double-poly six metal CMOS process and consumes 35mW from the supply of 1.8V. The proposed SSCG can generate 27MHz, 54MHz and 108MHz clocks with centre-spread ratios of +/-0.25%. The measured peak-to-peak cycle-to-cycle jitter is less than 100ps and the measured electromagnetic interference reduction amount is 2.8dB.