3D-IC design facilitates reduction in wirelength by vertically stacking dies. Through-silicon-vias (TSVs) are used to connect inter-die signals. However, big size TSV may result in large RC values significantly impacting the delay and power consumption in interconnects for 3D-IC. The RC values of TSV depend on TSV dimensions, technology and material. The impact of the TSV on the delay in 3D-IC depends on the length of the wire connected to it and metal layers assigned to these wires. The dynamic power consumption in 3D-interconnects include power consumption in wires, TSVs and buffers. The power consumption in buffers for inter-block signals require accurate estimation of delay in 3D-interconnect. Hence, it is crucial to consider RC values of TSV early in the design phase to evaluate and optimize electrical performance of 3D-IC. We propose TSV aware 3-D floorplanning to co-place circuit blocks and TSVs to evaluate and optimize footprint, wirelength, and electrical performance of inter-block connections. TSVs are arranged in islands with given dimension and pitch to ease computation of TSV capacitance. TSV aware 3D Floorplanning reduces peak and total delay in interconnects by 32% and 20% respectively. It also allows accurate estimation of buffers and reduction in interconnect dynamic power consumption by 7%.