Soft error has become one of the most critical reliability issues for nano-scaled CMOS designs. Many previous works discovered that the pulse width due to a particle strike on the device increases with temperature, but its system-level effect has not yet been investigated with statistical soft-error rate (SER). Therefore, in this paper, a combinational circuit (c17 from ISCAS'85) using a 45nm CMOS technology is first observed under different temperatures for SER. As a result, a SER increase (2.16X more) is found on c17 as the ambient temperature elevates from 25 ◦C to 125 ◦C. Second, along with growing design complexity, the operational temperatures of gates are distributed in a wide range and can be 2 to 3 times higher than the ambient temperature in reality. Therefore, we are motivated to build a temperature-aware SSER analysis framework that integrates statistical cell modeling to consider the ambient temperature (Ta) and the temperature variation (Tv), simultaneously. Experimental result shows that our SSER analysis framework is highly efficient (with multiple-order speed-ups) and accurate (with only <4% errors), when compared with Monte-Carlo SPICE simulation.