The proposed novel FinFET 7T cell involves the breaking-up of feedback between the true storing nodes that enhances the write-ability of the cell at ultra-low voltage (ULV) without boosted supply and write assist in 20nm FinFET technology. The read decoupling and feedback cutting makes proposed 7T more immune to process-voltage-temperature (PVT) variations in sub-threshold regime. Proposed 7T achieves 6% improved hold static noise margin (HSNM) as compared to the conventional iso-area 5T cell. The read margin (RM) is 18% higher than the 5T RM at 200mV. The Mean value of write ‘1’ static noise margin (WSNM) of 7T is 50% of VDD at 200mV while 5T fails. Moreover 7T has reduced read, write ‘0’ power consumption and write delay.