Circuit Design Perspectives for Ge FinFET at 10nm and Beyond

S. Sinha1,  L. Shifren2,  V. Chandra2,  B. Cline1,  G. Yeric1,  R. Aitken2,  B. Cheng3,  A. R. Brown3,  C. Riddet3,  C. Alexander3,  C. Millar3,  A. Asenov3
1ARM Inc., Austin, TX, 2ARM Inc., San Jose, CA, 3Gold Standard Simulations Ltd., Glasgow, Scotland


In this paper we study the circuit design implications of Ge vs. Si PMOS FinFETs at the 10 and 7nm nodes, using TCAD calibrated statistical compact models and the ARM predictive benchmarking flow. The ARM predictive flow incorporates advanced-node-relevant layouts, design rules, parasitic RC extraction and wire-loading. We present the first comprehensive simulation study evaluating Ge pFinFETs in a realistic circuit design context and show that the lack of a stressing mechanism, higher leakage and variability results in sub-optimal performance compared to Si in all circuit benchmark metrics.