Whereas contemporary Last Level Cache (LLC) designs occupy a significant fraction of total die area in chipmultiprocessors (CMPs), approaches to deal with the vulnerability increase of LLC against Single Event Upset (SEU) and Multi-Bit Upsets (MBUs) are sought. In this paper, we focus on reliability assessment of eDRAM LLC to propose a more accurate and application-relevant vulnerability estimation approach compare to conventional LLC SEU analysis methods. In particular, the eDRAM Bit Upset Vulnerability Factor (BUVF) is proposed and an algorithm is developed to assess the behavior of the under experiment benchmark suits against soft errors. BUVF explicitly targets the vulnerable portion of the eDRAM refresh cycle where the critical charge varies depend on write voltage, storage and bitline capacitance. Results for PARSEC benchmark suite indicated vulnerable sequences account for about 27.2% of data array lifetime in the cache, among which RR contributes about 23.4%. Furthermore, regardless of the size of the vulnerable data set located in RR sequence with short interval, this portion of cache space contributes negligible vulnerability to BUVF which is the result of spending a small fraction of program execution time in RR sequence. We recast the problem of reliable eDRAM LLC design as a straightforward search for reduced BUVF.