Ultra low power (ULP) applications use supply voltage (Vdd) scaling as an effective way of reducing power. However, as Vdd is scaled near the threshold voltage (Vt), increased variability limits the minimum Vdd and power that can be realized. This paper outlines a Veff variability framework to capture the total delay variation seen in digital circuits and describes its applicability for near-threshold delay variability analysis. The low-voltage variability framework has been validated against 14nm-FinFET ring oscillator (RO) measurements.