Negative capacitance-an unusual physical phenomenon, where the stored charge decreases with an increasing voltage-can find interesting applications in electronics. For example, when used as the gate oxide in the MOSFET, a negative capacitance material can reduce the subthreshold swing below the fundamental physical limit of 60 mV/decades. This device technology can, in turn, significantly lower the energy dissipation in CMOS circuits by enabling new pathways for arbitrarily reducing the power supply voltage. In the first part of talk, we will give an overview of the exciting developments in the field of negative capacitance over the past six years starting from the theoretical prediction in 2008 to the clean experimental demonstration of this phenomenon in archetypal ferroelectric oxides in 2015. I will also discuss our recent experimental work on negative capacitance transistors. In the second part, we will talk about energy and performance projections of circuits based on negative capacitance MOSFETs.