Beyond traditional bit truncation, recently proposed arithmetic and logic approximations have enriched the quality versus energy design space for custom hardware kernels in signal processing and other error-tolerant applications. Systematic exploration of such trade-offs requires fast, accurate, and generic quality-energy models that can drive datapath optimizations. Existing quality estimation approaches, however, are either based on slow simulation or limited in supported approximation types and quality metrics. In this paper, we propose a novel semi-analytical quality model that can predict a wide range of statistical metrics for arbitrary hardware approximations with deterministic error behavior. Input and error dependencies are captured using one-time error-free simulation only. Combining our quality estimation with a faithful energy model considering both switching activity and voltage scaling, we provide a complete quality-energy optimization flow. Optimization results for FFT and IDCT benchmarks show that our approach is 28x faster than purely simulation-based exploration, and 2x faster than existing hybrid approaches, all while achieving comparable estimation accuracy.