Memristor is one of the promising emerging non-volatile memory (NVM) technologies because it combines high endurance, scal-ability, and speed. However, process variation severely limits yields of memristor-based memories. In this paper we propose a yield-aware statistical design method for memristor cross-point memory systems under high process variations. This method jointly optimizes the per-formance and yield during the design procedure by choosing the optimal size of the cross-point arrays and peripheral circuits. To facilitate the proposed statistical design, we develop a novel analytical model to statistically characterize the read and write operations of memristor cross-point memory arrays, given the process variation model for each single memristive device. Then we use this model to accurately and efficiently estimate memory yield. We demonstrate the advantages of the statistical design using a yield-per-area optimization example.