Chair & Moderators:
Prof. Hai Li - University of Pittsburgh
Vinod Viswanath - Real Intent
On-chip Nonvolatile Memory Designs for energy-efficient IoT
Prof. Meng-Fan (Marvin) Chang, National Tsing Hua University (NTHU), Taiwan
Summary: Memory has become one of the bottlenecks in the development of IoT and wearable devices with low energy consumption. This tutorial addresses trends in the development of on-chip (embedded) non-volatile memory (NVM) for energy-efficient IoT applications. We will examine a variety of NVM technologies, including Flash, OTP/MTP, resistive RAM, phase-change memory (PCM), and STT-MRAM. This tutorial will explore the challenges faced by researchers in the design of low-power and high-speed circuits for on-chip NVM macros. We will also look at some state-of-the-art silicon-verified circuit techniques, including high-speed and low-voltage NVM macros. The implementation of NVM devices beyond conventional applications, such as nonvolatile-logics (nvLogics) and nonvolatile-SRAM/TCAM (nvSRAM/nvTCAM) for nonvolatile processors, will also be discussed.
About Meng-Fan (Marvin) Chang
Dr. Chang is a full Professor in the Dept. of Electrical Engineering of National Tsing Hua University (NTHU), Taiwan. Since 2011, he has also served as the Associate Executive Director of National Program for Intelligent Electronics (NPIE) in Taiwan. Dr. Change obtained considerable practical experience before joining NTHU in 2006, having spent more than ten years working in industry. Between 1997 and 2006, Dr. Chang worked in the development of SRAM/ROM/Flash macros/compilers at Mentor Graphics (New Jersey, US), TSMC (Taiwan), and the Intellectual Property Library Company (Taiwan). His research interests include circuit design for volatile and nonvolatile memory, 3D-Memory, spintronics and memristor logics, computing-in-memory, and circuit-device-interactions in non-CMOS devices. Since 2010, Dr. Chang has authored or co-authored more than 40 conference papers (including 11 ISSCC, 11 VLSI Symposia, 5 IEDM, 3 DAC papers) as well as 25+ IEEE journal papers. He also holds more than 25 U.S. patents and has been serving on technical program committees for IEDM, A-SSCC, ISCAS, VLSI-DAT, EDSSC, NVMSA, ISSCC, and numerous international conferences. He received the Academia Sinica Junior Research Investigators Award in 2012, the Ta-You Wu Memorial Award of National Science Council (NSC-Taiwan) in 2011, and the Outstanding Industrial Collaboration Award from NTHU in 2012. He has also received numerous awards from the Taiwan National Chip Implementation Center (CIC), the Macronix Golden Silicon Awards, and ITRI. He has been the Associate Editor of IEEE TVLSI, IEEE TCAD, and IEICE Tran. Electronics.
Pattern recognition and learning with neuromorphic cognitive systems
Prof. Giacomo Indiveri , University of Zurich, Switzerland
Summary: Artificial computing systems are vastly outperformed by biological neural processing ones for many practical tasks that involve sensory perception and real-time interactions with the environment, especially when size and energy consumption are factored in. One of the reasons is that the architecture of nervous systems, in which billions of neurons communicate in parallel mainly via asynchronous action potentials, is very different from that of today's mainly serial and synchronous logic devices and systems. Recent machine learning algorithms have taken inspiration from the nervous system to develop neuro-computing algorithms that are showing state-of-the-art performance in pattern recognition tasks. In parallel, different types of brain-inspired hardware architectures are being developed that reproduce some of the principles of computation used by the nervous system. These architectures represent a promising technology for both implementing the latest generation of neural networks, and for building faithful models of biological neural processing systems. In this tutorial I will present examples of spike-based neural network architectures that can be used to perform neural computation, signal processing, and pattern recognition. I will cover the design of large-scale networks of spiking neurons in VLSI technology, presenting a set of analog and digital electronic circuits that can be used to implement spiking neurons and spike-timing dependent plasticity learning synapses. I will show examples of VLSI neuromorphic information processing systems and present application examples that exploit their on-line learning properties.
About Giacomo Indiveri
Giacomo Indiveri is a Professor at the Faculty of Science of the University of Zurich, Switzerland. He obtained an M.Sc. degree in Electrical Engineering and a Ph.D. degree in Computer Science from the University of Genoa, Italy. Indiveri was a post-doctoral research fellow in the Division of Biology at the California Institute of Technology (Caltech) and at the Institute of Neuroinformatics of the University of Zurich and ETH Zurich, where he attained the Habilitation in Neuromorphic Engineering in 2006. He is an ERC fellow and an IEEE Senior member. His research interests lie in the study of real and artificial neural processing systems, and in the hardware implementation of neuromorphic cognitive systems, using full custom analog and digital VLSI technology.
Low Power SoC System Design – A Systems Approach to Power Management Techniques, Power and Performance Optimizations, Thermal and Energy Management of Systems-on-Chip
Rajiv Muralidhar , Senior Platform Architect, Intel Corporation
Summary: The last few years has seen the emergence of highly integrated embedded System-on-a-chip (SoC) architectures for several usages and platforms like high end mobile devices, tablets, smartphones and wearables. While each SoC component or accelerator can be optimized in various ways through the design phase, overall platform integration and platform power optimization is a growing challenge that is done in several different ways, specific to the final end system, operating system, and end usage intended for the device. Another trend has been the emergence of multi-core and multi-threaded architectures for all kinds of computing devices, ranging from cell phones, tablets, laptops, and netbooks, to high end computing systems, servers, etc. As the number of cores and threads-per-core increases, such systems present unique challenges in terms of scheduling, energy efficiency, temperature, heterogeneity, etc. Power management and optimization research in the last couple of decades has spanned multiple areas such as process technology, circuit/design optimizations, hardware, micro-architectural techniques for processors, caches, memories, dynamic voltage/frequency scaling of processors and other components, power management of individual components such as hard drives, external memories, and network interfaces, power-aware compiler optimizations, operating system optimizations for energy efficiency, and system/platform-wide power and thermal management. This tutorial covers end to end system design techniques from a power, energy and thermal perspective covering the most important energy efficiency techniques used in current generation Android, Chrome and Windows based smartphones, tablets, wearables and other small form factor devices.
About Rajiv Muralidhar
Rajeev Muralidhar is a Senior Platform Architect in Intel’s Mobile Communications Group, where he works on power management architectures for Intel SOC platforms. Previously, he worked in Intel Architecture Labs on network processor stacks, stability of internet routing and control plane protocols and quality of service for wired and wireless networks. Rajeev has been with Intel since 2000; he has a Bachelors from NIT, Surathkal (India) and Masters from Rutgers University, both in Computer Engineering. He is also a visiting researcher at Rutgers University’s NSF Center for Autonomic Computing, where he collaborates with researchers on power management in large many core systems.
Building Neuromorphic Computing Systems with Emerging Device Technologies
Dr. John Paul Strachan , Senior Research Scientist, Hewlett Packard Laboratories
Summary: Neuromorphic – or brain-inspired – computing is a multi-disciplinary field of research aimed at extending our computational capabilities to tackle traditionally difficult problems, including perception, decision-making, prediction, and sensorimotor control. There is added urgency with the simultaneously decreasing benefits of CMOS scaling and increasing data processing demands. Along with new neuromorphic architectures and algorithms, an important area of research goes down to the device level to attempt to mimic neural functions. There are a number of emerging device technologies that may be attractive candidates for this functionality, including memristors. This tutorial will survey the device level concepts and properties of memristors and how they can be applied to building future brain-inspired computing systems. Topics covered include the conceptual requirements for mimicking the nervous system with some of the open questions. Chua’s local activity principle will be introduced, how it underpins the generation of spiking behavior in neurons, and some physical realizations. Various examples of artificial neural networks and their implementations with emerging devices will be surveyed, including recurrent and convolutional neural networks, perceptrons, Hopfield networks, and associative memories.
About John Paul Strachan
John Paul Strachan is a Principle Researcher at Hewlett Packard Laboratories. He received a B.S. and M.E. at the Massachusetts Institute of Technology and a PhD in the Department of Applied Physics at Stanford University. After finishing a post-doc at Hewlett Packard Labs, he took a permanent position, joining a broad team of device physicists, materials scientists, architects, electrical engineers, and computer scientists to build future computing machines. His interests include using novel device technologies for applications in memory, computing, and sensing.