Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation due to NBTI. Various INC replacement algorithms have been proposed, but there are no evaluations for the necessity of the signal probability update and the aged delay calculation during optimization, which are highly CPU intensive. Also, the mitigation effectiveness and optimization time have not be fully evaluated. In this paper, strategies for selecting replacement candidates and the objective functions in optimization are evaluated using an example processor design. From the experimental result, it is found that the recalculation of the signal probability and the aged path delay greatly improves the optimization results. It is also found that the evaluated path limitation through path clustering with the average objective function reduces calculation time, without degrading the mitigation gain.