SHA-3 Implementation Using ReRAM based In-Memory Computing Architecture

Debjyoti Bhattacharjee, Vikramkumar Pudi, Anupam Chattopadhyay
Nanyang Technological University


Emerging non-volatile memory (NVM) technologies with computation capabilities can be effectively leveraged for computing tasks on resource-constrained Internet of Things (IoT) nodes. Redox-based Resistive RAM (ReRAM) is a promising NVM technology due to its high density, low leakage power and ability to perform functionally complete set of Boolean operations.

The secure transmission of IoT sensory data is of paramount importance to guard confidentiality and authenticity. However, encryption and authentication requires additional computing resources leading to significant performance overhead. An alternative approach, as explored in this current manuscript, is to use the in-memory computing capability of ReRAM. In particular, we study ReRAM based in-memory computing architecture for round function of cryptographic hash algorithm known as SHA-3 or Keccak. Our carefully done mapping reveals a bit/word-serial architecture for SHA-3. In that respect, the estimated throughput for ReRAM-based implementation is comparable to a highly optimized, bit-serial, lightweight CMOS realization.