Performance Evaluation of Copper and Graphene Nanoribbons in 2-D NoC Structures.

Ruturaj Pujari and Shaloo Rakheja
New York University


In this paper, performance models of different network on-chip (NoC) topologies are developed by a) incorporating physical models of the interconnect structures, and b) specifying the micro-architecture of cores and on-chip routers at 15 nm technology node for a clock frequency of 4 GHz. By incorporating device and interconnect models we implement a cross-layer design and optimization of the NoC architectures. The performance modeling is carried out for mesh, torus, and flattened butterfly (FBFLY) NoC topologies by focusing on global copper (Cu/low k) and graphene nanoribbons (GNRs) as the interconnect infrastructure for inter-core communication. The findings show that mesh NoCs incorporated with Cu/low or GNRs have the same latency metrics, while for torus and FBFLY NoCs, the high latency of GNR interconnects is prohibitive. Mesh, torus, and FBFLY topologies with GNRs as inter-core interconnects result in lower interconnect energy dissipation compared to Cu interconnects. The worst-case delay for mesh NoCs is equally governed by the on-chip router delay and inter-core interconnects delay but for torus and FBFLY NoCs, delay form inter-core interconnects particularly limits their performance. Therefore, ignoring the interconnect latency in the analysis overestimates the NoC performance significantly. We also determine the optimal network size up to which NoCs with GNR interconnects gives lower energy-delay product. The results achieved form this performance modeling are a representative of on-die implementations at 15 nm technology node which can be used to predict the realistic performance of a NoC.