A New Approach for Selecting Inputs of Logic Functions During Debug

Amir Masoud Gharehbaghi1 and Masahiro Fujita2
1The University of Tokyo, 2University of Tokyo


Debugging logic functions involves finding the function of some internals nodes such that their functionality becomes correct, according to the given specification. In some cases, different inputs are required for those internal nodes to be able to correct. In this paper, we propose an efficient method for selecting inputs of internal nodes during debug such that correction is guaranteed. Our method has a new different approach for debugging that focuses on finding the inputs of the functions without explicitly trying to find the new functions, by iteratively solving SAT problems until we find the inputs. Our experimental results on ITC'99 benchmarks shows the efficiency and effectiveness of our approach. The results shows more than 30% reduction in the number of SAT problems to be solved as well as more than 85% reduction in debug time, on average, compared to previous methods.