Composite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing

Shaahin Angizi1, Zhezhi He2, Ronald F. DeMara3, Deliang Fan3
1Department of Electrical and Computer Engineering, University of Central Florida, 2Department of ECE, University of Central Florida, 3University of Central Florida


Approximate Computing as a promising approach in Digital Signal Processing applications has been extensively analyzed to trade off limited accuracy loss for improvements in other circuit metrics, such as area, power, and speed. Most previous works on approximate circuit design have hardwired the degree of approximation in their implementations. This significantly limits their applicability, since inherent resilience varies significantly within applications. To address this limitation, in this paper, we propose a compact and energy efficient accuracy-configurable adder design based on a composite spintronic device structure consisting of magnetic domain wall motion stripe and magnetic tunnel junction. By leveraging the intrinsic current-mode thresholding operation of the spintronic device, we initially propose a hybrid Spin-CMOS majority gate and then we employ it to design an accuracy-configurable full adder cell. The proposed adder is equipped with a control knob to regulate energy-efficiency and the output quality trade-offs by modulating the circuit into two distinct operation modes (approximation and precision) to obtain acceptable output quality and reduced power consumption. The device-circuit SPICE simulations show 34.58% and 66% improvement in power consumption for precision and approximation modes, respectively, over recently reported Domain Wall Motion-based full adder design. The area-efficient accuracy-configurable adder also exhibits 19% improvement in device count complexity over state-of-the-art CMOS FA design. We demonstrate the efficacy of our proposed adder in discrete cosine transform computation for a digital image processing architecture.