As chip complexity continues to grow, simulation-based functional verification is becoming a bottleneck for the overall chip design cycle. This problem can potentially be mitigated by machine learning-guided stimulus generation that attains verification coverage with considerably reduced simulations. The effectiveness of the machine learning approach was originally confirmed in prior research, which was restricted to coarse-grained test level optimization. We will demonstrate the limitations of test-level optimization in some common cases, and propose using a fine-grained transaction level optimization approach as a superior alternative. Experimental results show that our techniques can potentially reduce the verification coverage closure time by as much as 70%.