27^th International Symposium on Quality Electronic Design (ISQED'26) Call for Papers

For any question please contact the publication committee by sending email to isqedisqed@gmail.com. Note the following important dates:

IMPORTANT DATES (Midnight, US Pacific Time)
Paper Submission Deadline	Sept. 17, 2025
Acceptance Notification	Jan. 22. 2026
Camera-Ready Paper Due	Feb 17, 2026
Presentation Video, and Speaker Bio	March 20, 2026

Papers are requested in the following areas

A pioneer and leading multidisciplinary conference, ISQED accepts and promotes papers related to the manufacturing, design and EDA. Authors are invited to submit papers in the various disciplines of high level design, circuit design (digital, analog, mixed-signal, RF), test & verification, design automation tools; processes; flows, device modeling, semiconductor technology, advance packaging, and biomedical & bioelectronic devices. All past Conference proceedings & Papers have been published in IEEE Xplore digital library and indexed by Scopus.

The details of various topics of paper submission are as follows:

EDA Tools and Methodologies & Agentic AI (EDA)

Agentic AI for Electronic Design and Design Automation (AI): Systems and hardware enabling autonomous, goal-driven AI agents, including cognitive computing, neuromorphic architectures, and secure AI accelerators. Covering design, implementation, and applications in intelligent interaction and cognitive environments.
EDA tools, design flows, and physical design methodologies for digital, analog, and mixed-signal systems
Tools for analyzing and mitigating variation, aging effects, and soft errors
Design, verification, and maintenance of hard and soft IP blocks
Integration, testing, qualification, and manufacturing of IP from diverse vendors
EDA tools for emerging application domains such as smart power grids and renewable energy systems
Design automation methodologies for 3D ICs, heterogeneous integration, and advanced packaging
Modeling and simulation of semiconductor devices and processes (TCAD)
CAD techniques for bio-inspired and neuromorphic computing systems
EDA tools and methods for photonic devices, circuit, and system design
EDA for MEMS and other micro/nano-scale systems
Other topics related to design automation tools, platforms, and methodologies

Hardware and System Security (HSS)

Attacks and countermeasures, including side-channel attacks, reverse engineering, hardware Trojans, and physical tampering
Hardware-based security primitives such as physically unclonable functions (PUFs), true random number generators (TRNGs), and lightweight cryptographic ciphers
Security, privacy, and trust protocols; secure information flow; and trusted execution environments
Trust establishment using untrusted tools, third-party IP, AI/ML models, and fabrication/manufacturing services
Secure hardware architectures and memory systems
Post-quantum cryptographic and security primitives for hardware platforms
Security challenges and design opportunities in emerging nanoscale devices and technologies
Internet of Things (IoT) and cyber-physical system (CPS) security at the hardware and system levels
Other topics related to hardware, embedded, and system-level security

Design Test and Verification (DTV)

Formal, assertion-based, simulation-based, and hybrid verification techniques for hardware and software systems
Design-for-Testability (DFT), Automatic Test Equipment (ATE), and Built-In Self-Test (BIST) for digital, analog/mixed-signal, SoC, and memory components
Test synthesis and synthesis-for-testability for improved coverage and quality
Fault diagnosis, IDDQ testing, novel test methods, fault modeling, ATPG, and DPPM prediction
SoC and IP testing strategies, including hierarchical and system-level test approaches
Design methodologies linking testability to manufacturing and yield improvement
Hardware/software co-verification and co-validation strategies
Advanced verification methodologies and testbenches, including UVM, HDLs, and HVLs
Formal and semi-formal validation techniques supporting functional safety and security
Self-checking testbenches and novel methods for analog/mixed-signal verification
Any other emerging topics related to design test and verification

Emerging Device and Process Technologies and Applications (EDPT)

Design, simulation, and modeling of emerging solid-state devices and materials
Emerging non-volatile memory and logic technologies, such as STT-RAM, PC-RAM, RRAM, and memristors
Applications of emerging devices in advanced computing domains including cognitive, neuromorphic, and quantum computing
Qubit technologies and quantum circuits for quantum information processing
Specialty device technologies, including MEMS, NEMS, and other nanoelectronic devices
Design-Technology Co-Optimization (DTCO) methodologies across ASIC, FPGA, RF, memory, and custom/semi-custom designs
Advanced-node manufacturing techniques, including EUV lithography, DSA, and multiple patterning
Advanced interconnect solutions such as air-gap structures and silicon photonics
Modeling and optimization of emerging technology impact on power, performance, area, cost, and reliability
Design methods and tools for improving yield, manufacturability, and process robustness
Other topics relevant to emerging device, process, and integration technologies

Circuit Design, 3D Integration and Advanced Packaging (ICAP)

Low-power, high-performance, and reliable design of digital, analog, RF, memory, interconnect, programmable logic, and FPGA circuits
Techniques for leakage reduction, dynamic/static power optimization, and power management
Analog and mixed-signal circuit design, including all-digital PLLs/DLLs, ADCs, and DACs
Adaptive and resilient circuit techniques for variability and fault tolerance
On-chip sensors and monitors for process, voltage, temperature, and aging variations
Hardware design for IoT systems, including digital logic, memory, wireless interfaces, energy harvesting, signal processing, and power management
Advanced packaging technologies including 3D ICs, 2.5D interposers, and multi-chip modules and their impact on design methodologies
Design techniques and flows for vertically integrated circuits and chips
Modeling and mitigation of inter-die and inter-layer interactions in 3D ICs
Design of die-to-die and chip-to-chip interfaces for 2.5D/3D integration
Design-for-testability, yield enhancement, and system-level design considerations in 3D/2.5D ICs
Die-package co-design and integration challenges
Other topics related to circuit design, 3D integration, and advanced packaging technologies

System-level Design and Methodologies (SDM)

Design methods for complex systems including multi-core processors, embedded systems, SoCs, GPUs, accelerators, and heterogeneous architectures
System-level trade-off analysis and multi-objective optimization (e.g., yield, power, performance, area, and cost)
Power and thermal management techniques at the system level
Modeling and simulation frameworks to assess the impact of process, voltage, temperature, and aging variations on system performance and reliability
System-level implications and integration of emerging technologies
Cyber-Physical Systems (CPS): design methodologies, tools, and reliability analysis
Hardware/software co-design, co-simulation, co-optimization, and design-space exploration
Prototyping and emulation of hardware/software systems using FPGAs
Microarchitectural transformations and optimization techniques
System communication and interconnect architecture, including Network-on-Chip (NoC) methodologies
Application-driven design of heterogeneous computing platforms
Any other topics related to system-level design, modeling, and co-optimization

Cognitive Computing Hardware (CCH)

Neuromorphic computing, non-Von Neumann architectures, and brain-inspired hardware paradigms
Hardware and architectures for neural networks, including deep learning and spiking neural networks
Neural network acceleration using GPGPUs, FPGAs, dedicated ASICs, and custom silicon
Cognitive-inspired computing systems and fundamentals for intelligent information processing
AI-assisted cognitive computing methods and hardware/software co-design approaches
Hardware support for secure and reliable machine learning and cognitive applications
Cognitive computing in large-scale systems: big data processing, sensing, and interaction
Brain analysis and neuroscience-driven models for hardware design
Internet of Cognitive Things, cognitive environments, and data-driven sensing systems
Cognitive robots, intelligent agents, and edge intelligence platforms
Security and trust challenges in cognitive-inspired computing systems
Testbeds, prototype implementations, and emerging applications of cognitive hardware
Other topics related to cognitive and intelligent computing hardware

Submission of Papers

Paper submission must be done on-line through the conference web site: www.isqed.org. The guidelines for the final paper format are provided on the conference web site. Authors should submit original, unpublished papers along with an abstract of about 200 words. The manuscripts should be at least four (4) pages long but not exceed eight (8) pages, should not use smaller than 10pt font size, and must be consistent with the format provided in the conference website: www.isqed. org. The manuscripts longer than 10 pages and/or written in less than 10-pt font sizes will not be reviewed. To permit a blind review, do not include name(s) or affiliation(s) of the author(s) on the manuscript and abstract. The complete contact author information needs to be entered separately.
The manuscripts identifying the name and/or affiliations of the authors in the submitted manuscript will be rejected without review. Please check the as-printed appearance of your paper before sending your paper. In case of any problems email isqedisqed@gmail.com.

See the MS Word template at the bottom of this page. Use the on-line paper submission procedure by clicking the following link: ON-LINE. If you have problem accessing the paper submission site it is located at: https://softconf.com/p/isqed2026

Work in Progress (WIP) Submission

Ongoing research projects can be presented at ISQED under the Work in Progress (WIP) category. This provides a unique opportunity to authors to receive early feedback on their current work. For more information please click HERE.

Workshop/Tutorial Proposals

Several workshop/tutorial sessions will be held on the first day, and would offer valuable opportunities for practicing professionals to refresh or upgrade their skills in quality-based IC design techniques, methodologies and tools. These sessions are intended to supplement the conference by providing in depth, practical and proven design solutions. Workshops/Tutorials will be taught by experts in the field, who are intimately involved with the issues and solutions in their perspective areas, from both industry and academia. If interested in offering a tutorial, please send your tutorial proposals to the ISQED workshop/tutorial committee to isqedisqed@gmail.com

The proposal should include:

Title of Workshop/Tutorial
Name of organizer
Name(s), address, and affiliation of the Moderator
Name(s), address, and affiliation of presenter(s)
Half-page summary of each presenter's biography

You may send your proposal by email as text or as an Adobe PDF file. The presentations must be technical, up to date, relevant, and target the design community. Marketing presentations will not be accepted. In order to meet the conference timeline, we would like to have your proposal no later than Nov. 22, 2025. Please check the archive section of the web site for a listing of past tutorials.

Templates and Resouces for Authors & Speakers

ISQED

27th International Symposium on Quality Electronic Design (ISQED'26) Call for Papers

IMPORTANT DATES (Midnight, US Pacific Time)