Design for
Manufacturability/Yield & Quality
DFM/DFY/DFQ
definitions, methodologies, matrices, and standards. Quality-based design
methodologies and flows for custom, semi-custom, ASIC, FPGA, RF, memory,
networking circuit, etc. Design flows and methodologies for SoC, and SiP.
Analysis, modeling, and abstraction of manufacturing process parameters
and effects for highly predictable silicon performance. Design and
synthesis of ICs considering factors such as: signal integrity,
transmission line effects, OPC, phase shifting, and sub-wavelength
lithography, manufacturing yield and technology capability. Design for
diagnosability, defect detection and tolerance; self-diagnosis,
calibration and repair. Design and manufacturabilty issues for Digital,
analog, mixed signal, RF, MEMS, opto-electronic, biochemical-electronic,
and nanotechnology based ICs. Redundency and other yield improving
techniques. Global, social, and economic implications of design quality. |
Design
Verification and Design for Testability
Hardware and Software, Formal and simulation based design verification
techniques to ensure the functional correctness of hardware early in the
design cycle. DFT and BIST for digital and SoC. DFT for
analog/mixed-signal ICs and systems-on-chip, DFT/BIST for memories. Test
synthesis and synthesis for testability. DFT economics, DFT case
studies. DFT and ATE. Fault diagnosis, IDDQ test, novel test methods,
effectiveness of test methods, fault models and ATPG, and DPPM
prediction. SoC/IP testing strategies. Design methodologies dealing with
the link between testability and manufacturing. |
System-level Design, Methodologies & Tools
Emerging
system-level design paradigms, methods and tools aiming at quality. ESL
design process and flow management. System-level design modeling,
analysis, synthesis, estimation and verification for correct high-quality
hardware/software systems. Development of reliable, responsive, secure,
manufacturable, and defect-tolerant systems. New concepts, methods and
tools addressing the hardware and system design complexity, multitude of
aspects, manufacturability, and usage of technology information and
manufacturing feedback in the system-, RTL- and logic level design. The
influence of the nanometer technologies’ issues on the system-, RTL- and
logic-level design. System-level trade-off analysis and multi-objective
(yield, power, delay, area …) optimization. Effective and efficient
development, implementation, analysis and validation of large SoCs
integrating IP blocks from multiple vendors. Global, social, and
economical implications of Electronic System and Design Quality. Emerging
standards and regulations influencing system quality. |
EDA Methodologies, Tools, Flows & IP Cores;
Interoperability and Reuse
EDA
tools addressing design for manufacturing, yield, and reliability.
Management of design process, design flows and design databases. EDA tools
interoperability issues and implications. Effect of emerging technologies,
processes & devices on design flows, tools, and tool interoperability.
Emerging EDA standards. EDA design methodologies and tools that address
issues which impact the quality of the realization of designs into
physical integrated circuits. IP modeling and abstraction. Design and
maintenance of technology independent hard and soft IP blocks. Methods and
tools for analysis, comparison and qualification of libraries and hard IP
blocks. Challenges and solutions of the integration, testing, qualifying,
and manufacturing of IP blocks from multiple vendors. Third party testing
of IP blocks. Risk management of IP reuse. IP authoring tools and
methodologies.
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Power-conscious
Devices, Interconnects, and Circuits
Device, substrate, interconnect, circuit , and IP block modeling and
simulation techniques; CMOS, Bipolar, and SiGe HBTs device modeling in
the context of advanced digital, RF and high-speed circuits. Modeling and
simulation of novel device and interconnect concepts. Signal integrity
analysis: coupling, inductive and charge sharing noise; noise avoidance
techniques. Modeling statistical process variations to improve design
margin and robustness, use of statistical circuit simulators. Power grid
design, analysis and optimization; timing analysis and optimization;
thermal analysis and design techniques for thermal management.
Power-conscious design methodologies and tools; low power devices,
circuits and systems; power-aware computing and communication;
system-level power optimization and management. Design techniques for
leakage current management. Design of robust 3D Integrated Circuits.
Successful applications of TCAD to circuit design. Impacts of process
technologies on circuit design and capabilities (e.g. low-Vt transistors
versus increased off-state leakages) and the accuracy, use and
implementation of SPICE models that faithfully reflect process
technologies.
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Package - Design
Interactions & Co-Design
Concurrent circuit, package, and PCB/PWB design and effect on quality. EDA
tools and methodologies dealing with the IC Packaging electrical and
thermal modeling and simulation for improved quality of product. SoC
versus system in a package (SiP): design and technology solutions and
tradeoffs; MCM, BGA, Flip Chip, and other innovative packaging techniques
for various applications such as mixed-signal and RFIC.
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Design of Reliable
Circuits and Systems
Device and process reliability issues and effect on design of reliable
circuits and systems. ESD design for digital, mixed signal and RF
applications. Exploration of critical factors such as noise, substrate
coupling, cross-talk and power supply noise. Significance and trends in
process reliability effects such as gate oxide integrity,
electromigration, ESD, etc., and their relation to electronic design.
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Physical Design, Methodologies & Tools
Physical design for manufacturing; Physical synthesis flows for
correct-by-construction quality silicon, implementation of large SoC
designs. Tool frameworks and data-models for tightly integrated
incremental synthesis, placement, routing, timing analysis and
verification. Placement, optimization, and routing techniques for noise
sensitivity reduction and fixing. Algorithms and flows for harnessing
crosstalk-delay during physical synthesis. Tool flows and techniques for
antenna rule and electromigration rule avoidance and fixing. Spare-cell
strategies for ECO, decoupling capacitance and antenna rule fixing.
Physical planning tools for predictable power-aware circuits. Reliable
clock tree generation and clock distribution methodologies for Gigahertz
designs. EDA tools, design techniques, and methodologies, dealing with
issues such as: timing closure, R, L, C extraction, ground/Vdd bounce,
signal noise/cross-talk /substrate noise, voltage drop, power rail
integrity, electromigration, hot carriers, EOS/ESD, plasma induced damage
and other yield limiting effects, high frequency effects, thermal effects,
power estimation, EMI/EMC, proximity correction & phase shift methods,
verification (layout, circuit, function, etc.).
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Emerging/Innovative Process & Device Technologies and Design Issues
Emerging processes & device technologies and implications on IC design
with respect to design’s time to market, yield, reliability, and
quality. Emerging issues in DSM CMOS: e.g. sub-threshold leakage, gate
leakage, technology road mapping and technology extrapolation techniques.
New and novel technologies such as SOI, Double-Gate (DG)-MOSFET,
Gate-All-Around (GAA)-MOSFET, Vertical-MOSFET, strained CMOS,
high-bandwidth metallization, 3D integrated circuits, nanodevices, etc.
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Management of Design
Database, Design Process, and Tools Interoperability Implications
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Global, Social, and
Economical Implications of Design Quality
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