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Industry Must Turn Its Attention to Quality
Ali
Iranmanesh
ISQED Founder and
Chairman
February 20, 2000
During the past 20 to
30 years, we have witnessed a phenomenal increase in the level of device
scaling as well as in semiconductor manufacturing quality. This has
enabled the industry to provide ever more complex electronic products.
However, the advancement in semiconductor technology has drastically
surpassed the progress in the capability and quality of EDA tools and
design methodologies. The result is a fast-growing disparity between the
available capability and what can be realized in design practice. The
EDA industry's focus should therefore be not just in the traditional
areas of performance, timing, area and power specification, but also in
product yield, reliability, and manufacturability.
Design-for-reliability, design-for-yield, and design-for-manufacturing
should be integral parts of the modern design methodology. These,
together with time-to-market considerations and performance, form the
foundation of the quality electronic design. To achieve these targets,
close coordination and cooperation among various disciplines involved in the
design, development, and manufacturing of integrated circuits and
systems are essential. In the late 20th
century, the quality revolution in manufacturing led to phenomenal
progress in semiconductor technology. The early 21st century will usher
in the age of industry maturity, where these principles are successfully
applied toward EDA tools, methodologies and processes.
Slap
It Together And Ship It!
Aart
J. de Geus
Chairman & CEO, Synopsys Inc.
ISQED 2000, March 21, 2000
In
today’s world of e-commerce and dot-com instant business successes,
time to market constraints have taken the upper hand in almost all
product decisions. In that scenario, what happens to the role of quality
in the design of semiconductors and electronic systems? In his keynote, Aart de Geus addressed the trade-offs of “market” needs vs.
“quality” needs and showed that what appears to be a trade-off may
not be one at all.
The
Practical Side of Quality
John
East
CEO, Actel Corporation
ISQED 2000, March 21, 2000
My practical
definition of quality is getting it right the first time, on time. The
downsides of poor quality work
need no explanation. Unfortunately, though, the consequences of being
late to market can doom any potential market advantage. The only sure
win comes when the product is both high quality and on time. To help
assure on-time delivery of working ICs, I advocate “two-handed
management.” This means with one hand, do the job as best you can
using the tools and techniques available, but with the other hand, take
steps to see similar jobs are done better and faster the next time. An
example of twohanded management in the distant past was the development
of various simulation techniques. The two-handed manager of the future
will look for silicon with advanced capabilities in the areas of “observability,”
“tweakability” and incremental specification techniques as well as
inherent improvements in speed, power and cost.
Design
for Quality and Manufacturing
Prakash
Agrawal
CEO, NeoMagic
ISQED 2000, March 21, 2000
This
presentation will discuss from a CEO’s perspective the process needed
to design a quality chip for manufacturing. It will cover the milestones
necessary for bringing a successful chip to market. Discussion
highlights will focus first on a well thought out analysis of market
requirements, taking into account the product roadmaps and feature
requirements of your major customers, the competition, the potential market
size, and the delivery schedule necessary to hit the window of
opportunity to sell the new product. Next, it will focus on how to
proceed with a thorough evaluation of your company’s internal
variables, such as your technology roadmap, cost analysis, capability of
strategic partners, capacity requirements, and return on investment.
Finally, it will give tips on evaluating the results of matching the
market requirements with your company’s internal capabilities. It will
mention some of the well-known design tools and practices used in the
industry that can help you assure the built-in quality
necessary to meet manufacturing standards and market needs.
Ramping
New IC Products in the Deep Sub-micron Age
John
Kibarian
CEO, PDF Solutions
ISQED 2000, March 21, 2000
It
is well known that the majority of the potential profits are early in a
products life. This is especially true in product segments such as
system on a chip, graphics accelerators, microprocessors, and memory.
The spoils in these segments go the company who gets its product to
market first. At the same time, the investments required to produce the
next generation products is going up at an accelerated pace. As a
result, companies are sharing the investment by working with more third
party suppliers. Today, a chip will be designed with 3rd party EDA tools
and using commercial IP. It is often manufactured in commercial
foundries, and tested and assembled a separate company. When the product
is not meeting
yield and performance, how are the issues resolved? Eventually, these
yield issues are resolved, but often not before the profitable part of
the product’s lifecycle is complete. In this presentation we describe
new methodologies, tools and services which can help turn designs into
products. We will summarize the key technical issues which make
performance and yield targets difficult to meet given the product’s
lifecycle constraints and demonstrate how these new methodologies can
greatly change the production ramp. Examples of these methods applied to
advanced products such as microprocessors, embedded DRAM, and system on
a chip, and DRAM will be provided.
Platform-based
Design: A Path to Efficient Design Re-Use
Alberto
Sangiovanni-Vincentelli
Prof.,
UCB
ISQED 2000, March 22, 2000
System
design is undergoing a series of radical transformations to meet
performance, quality, safety, cost and time-to-market constraints
introduced by the pervasive use of electronics in everyday objects. An
essential component of the new system design paradigm is the
orthogonalization of concerns, i.e., the separation of the
various aspects of design to allow more effective exploration of
alternative solutions. Since the mask set and design cost for Deep
Sub-Micron implementations is predicted to be overwhelming, it is
important to find common architectures that can support a variety of
applications.
In
this talk, we will explore methods for selecting families of software
and hardware architectures that allow a substantial design re-use and
some paradigms for embedded system designs that are likely to become the
pillars of future tools and flows.
Embedded-Quality
for Test
Yervant
Zorian
Chief
Technology Advisor, LogicVision
ISQED 2000, March 22, 2000
The
basic concept of embedding test functions onto the very IC design is a
simple one. However, the complexity offered by the emerging
system-on-chip and the very deep micron technologies has created
difficult challenges and quality risks. A new wave of embedded, quality
insurance functions, are needed to address this complexity level. This
talk will discuss such design for quality trends and solutions and will
analyze their impact not only on go/no-go test, but also on a set of
expanded quality insurance functions to support debug, measurement,
diagnosis and repair.
Deep
Submicron ULSI Design Paradigm: Who is writing the future?
Kamran
Eshraghian
Prof.,
Edith Cowan University
ISQED 2000, March 22, 2000
The
concept of “ technology
generation” attributed to Gordon Moore has
created a plausible method for predicting the behavior of technology
road map that has seen world’s production of silicon CMOS to exceed
75% of electronic related materials. A feature of such progress is
characterized by the complexity factor that predicts the emergence of a
new generation of technology every three years. A reasonable method of
comparison would be to observe the parallel between CMOS based systems
with those of biologically inspired systems. Deep submicron, synonymous
with Ultra Large Scale of integration, suggests that by the year 2010
the number of transistors/chip will be in the order of 0.5x109, with an
intrinsic clock speed of 3GHz. At this level of integration the classic
MOS transistor would have only a few ‘electrons’ in the channel to
direct. Thus, the reality of Quantum MOS (QMOS) transistor becomes a
plausible possibility. In the mean time the question remains as to how
are we going to cope with the design and quality of the new system
complexity. ULSI design requires a shift in
the design paradigm from current evolutionary thinking for system
integration, to more of revolutionary approaches as depicted by
attributes of “brain architecture”.
Future
Platform for Mobile Communication
Hajimi
Sasaki
Chairman
of the Board, NEC
ISQED 2001, March 27, 2001
This
keynote would explore three driving forces in the IT revolution that are
actualizing an Information Society: first, the Internet global, ever
expanding nature and second, the ability to create the ultimate personal
information tool. And last, at the heart of these forces is the
cutting-edge semiconductor device. Especially in mobile where products
are composed primarily of semiconductors, we see that the creation
of advanced semiconductor devices controls to a large degree the
superior nature of the mobile product. Mobile products must balance many
constraining criteria such as size and weight against functionality such
as low power consumption. There are also a wide array of technologies involved
such as low power consumption circuit design, flash memory and RF power
device. Additionally, intellectual property has become even more important.
Moreover, the harmonization of semiconductor technology and peripheral
technologies such as smallscale, light-weight packaging technology, long
life rechargeable batteries and flat panel displays has become an
important factor.
Delivering
Quality Delivers Profits
Joe
Costello
CEO,
think3
ISQED 2001, March 27, 2001
The
future of electronics is SoC design. SoC design complexity is
accelerating due to rapid change on multiple dimensions: design content,
deep sub-micron (DSM) electrical and physical effects, and the sheer
scale of SoC projects. At the same time, market windows are dramatically
decreasing. These fundamental technology trends and economic forces
underscore the need to rethink conventional design methodology and
conventional business practices for SoC design delivery. An SoC design
foundry, combining a fast and scalable mixed-signal SoC design
methodology with innovative design technology and electrical engineering
expertise, enables not only the timely delivery of SoC designs, but also
robust design quality through electrically correct silicon engineering.
The
Expanding Use of Formal Techniques in Electronic Design
Raul
Camposano
CTO/GM,
Synopsys, Inc.
ISQED 2001, March 27, 2001
Although
Electronic Design Automation (EDA) tools allow some tolerance for
features having only limited scope or not working in all cases, there is
no tolerance for error in their final results. Since the beginning, EDA
tools have included so-called "formal" techniques to ensure
such error-free results.
More
and more, formal verification tools are being adopted as a necessary
part of mainstream design flows to tackle the exploding verification
challenge. In this keynote address, we will focus on some of these
formal techniques; in particular, equivalence checking, property
checking, and the combination of simulation with formal techniques --
all of which play an important role in creating zero-defect results in
state-of-the-art electronic design.
IC Design Methodology
in the Foundry Era: Introducing ‘Heads-Up’ Design”
Edward
C. Ross
President, TSMC, USA
ISQED 2001, March 27, 2001
The
emergence of the foundry as a primary semiconductor manufacturing
resource has created a seachange in the way EDA companies interact with
manufacturers. Since the key concern for many foundry customers is
time-to-volume, EDA companies are now focused not just on system-level
design, but on “heads-up” design, e.g., bringing to designers the
ability to build whole systems at the speed of thought. Dr. Ross
discusses emerging trends in the EDA, IP, library and design center
communities, wherein deep collaboration with foundries is producing a
variety of Internet-based solutions that are revolutionizing IC design
methodologies.
Quality of Design from
an IC Manufacturing Perspective
Wojciech
P. Maly
Professor,
Carnegie Mellon University
ISQED 2001, March 28, 2001
There
are many credible sources (including the ITRS) now seeing cost of IC
manufacturing as a potentially negative factor that may affect the
future of the IC industry. There are also a number of answers to the
growing-cost-of-manufacturing challenge. One of them is IC design for
efficient manufacturing -- measured by such indices as yield,
time-to-volume, etc. The first objective of this presentation is to
analyze publicly discussed visions for the IC industry and derive from
them manufacturability conditions that must be met for these visions to
materialize. We will focus our discussion on the recent version of the
ITRS. It will be shown that ITRS predictions cannot be fulfilled by
design or manufacturing approaches alone. Only by solving complex
trade-offs on the design-test-manufacturing interface one may provide a
chance to overcome the rising-cost-of manufacturing problem -- the main
stumbling block on the ITRS horizon. The second objective of
the presentation is to propose a redefinition of the notion of the
quality of IC design, so it can accommodate manufacturability measures
as primary design goals in addition to traditional die size, performance
and time-to-first-silicon design quality indices. Such a re-definition
is possible and maybe necessary contribution of the IC design community
in addressing the rising-cost-of manufacturing problem.
Embedded Test Leads to
Embedded Quality
Vinod
Agrawal
CEO,
Logic Vision
ISQED 2001, March 28, 2001
The
concept of embedded test, wherein physical test engines are built right
on to the semiconductor chip, has a very strong quality value throughout
the lifecycle of the chip. These embedded testers can be reused
throughout the lifetime of the chip from silicon debug, to
characterization, to production testing (both wafer probe and final
test), to board prototyping, to system integration and then finally to
the diagnosis in the field. More than 50 semiconductor and system
companies world-wide are already using embedded test in their complex
chips, to gain significant quality, cycle time and economic competitive
advantage. This talk will explore how embedded test is becoming a
standard choice for IC and system developers.
Quality on Time
Aki
Fujimura
COO and President, Simplex*
ISQED 2001, March 28, 2001
(*Simplex
was acquired by Cadence in 2002)
How is it that a group of talented,
highly motivated, hard-working software engineers consistently produce
low-quality software, late? It is the speaker's view that schedule
management and quality management go hand in hand. The traditional
thinking that quality and schedule are tradeoffs is exactly the approach
to engineering management
that starts the downward spiral resulting in organizations that can
never deliver quality software nor on-time delivery. The talk discusses
the notion that schedules are probability distributions, and presents
several practical quality and schedule management techniques.
Quality of SoC designs
through quality of the design flow: Status and Needs
Philippe
Magarshack
Vice
President, Central R&D Group and Director, Design Automation, STMicroelectronics
ISQED 2001, March 28, 2001
It
is now universally recognized that System-on-Chip (SoC) is the
appropriate product solution to meet the demand of cost and volume for
many electronics markets. The increasing pressures coming from shrinking
market windows, accelerating process roadmaps and increasing mask costs,
render necessary that SoC be correct at first silicon.
This is becoming a considerable challenge due to the complexity of
systems that can be built on the same chip: current process capabilities
are approaching 100 million devices. Additionally, this level of
integration comes at the price of renewed parasitic effects, such as
crosstalk, voltage drop and electro-migration.
A
complex design flow is necessary to solve these conflicting trends,
combining executable specifications, isolating function from
communication, exploring architectures and trading off speed, power,
area and schedules, and finally a fast route to implementation, be it in
software running on embedded processors, dedicated digital hardware, or
dedicated analog cells. The successive levels of abstraction of the
system description warrant the need for extensive verification of the
SoC, both at functional level, and at the timing, power and reliability
levels. Building such a design flow calls for mixing very good point
tools, coming from established EDA vendors as well as start ups and
academia. But above all, it requires well-defined and structured
interfaces between tools at key hand-off points in the design flow.
Standard design languages and Application Programming Interfaces (API's)
are fundamental to the success of SoC.
IP
REUSE QUALITY: “Intellectual Property” or “Intense Pain”?
John Chilton
Sr. VP and General Manager
Synopsys, Inc.
ISQED 2002, March 19, 2002
As
systems on a chip become more complex, reuse of third-party intellectual
property (IP) becomes more necessary to meet time-to-market deadlines.
However, issues surrounding IP quality are very much unresolved. Poor IP
quality is the key reason why many IP users feel that “IP” is
actually an acronym for “Intense Pain.” . There are major
inconsistencies surrounding basic quality, including fully synchronous
design, registered inputs and outputs for IP blocks, and completion of
full specifications before design. All these inconsistencies contribute
to difficulties in using the IP and integrating it into a chip design.
One of the key reasons why quality is still such an issue within the IP
community is the issue of “reuse” versus “salvaging.” Much of
the IP sold over the last few years wasn’t really designed for reuse.
Instead, it was designed for use in a single chip, then later repackaged
(i.e., salvaged) as IP. There has also been tremendous interest in
creating IP repositories—fancy Java based, Web-accessed, and
multi-featured custom products meant to hold the wealth of IP. Along the
way, though, we forgot to create enough fully reusable IP to warrant
these repository investments. Although the challenges in the IP business
may seem daunting (and there are many more besides just those that
concern quality), they are well worth the effort when you consider the
rewards. There’s a tremendous need for IP to address the growing
productivity gap, which represents a great opportunity for the
third-party IP industry.
Why
Integrated Yield Management is a Necessity
Y.
David Lepejian
President, CEO and
Chairman HPL
ISQED 2002, March 19, 2002
Improving
semiconductor yield is a multi-facetted process that must include
design, manufacturing, and test. An integrated approach enables
companies to rapidly reach higher levels of revenue and profitability.
Incorporating design-for-yield concepts early, improving the quality of
the test programs, and applying new technology to accelerate the
measurement and correction of failure sources in the production process
combine to have powerful effect upon company profits, product quality,
and time to volume.
Design
Success: Foundry Perspective
Jim Kupec
President, UMC USA
ISQED 2002, March 19, 2002
Leading
edge foundries are rolling out new process technologies every two years
with today’s advance processes capable of producing a quarter billion
transistor on a thumb nail sized chip. The growth of the fabless
business model has enabled many companies to organize and build value
with the strength of their design capabilities. Quality is often
reflected by the continued success of design practices resulting in
market success. The many styles of design implementations provided by a
large number of companies sharing a common process helps provide a
Darwinian view of quality practices. The interaction with design flows,
libraries, special purpose IP, memory types are important
considerations. This talk will address the trade-offs and successful
design technologies used in foundries.
What
you don’t know CAN hurt you: Designing for survival in a
sub-wavelength environment
Y.C.
(Buno) Pati
President and CEO,
Numerical Technologies
ISQED 2002, March 19, 2002
The
semiconductor industry’s promise to deliver an endless array of chip
designs to match the voracious appetite for smaller, faster, cheaper
devices is in danger of ringing hollow. We could make this commitment
with confidence up to recently. But, lately we’ve hit the wall.
We’re crashing through the sub-wavelength barrier and we’re feeling
our way toward
designing and manufacturing chips in a challenging new environment
without benefit of some key process technologies. Now, to survive and
thrive, chipmakers are turning to phase shifting—just a novel, clever
concept a few short years ago—as a critical and necessary enabler of
producing integrated circuits at dimensions of 0.13 micron and below.
Inevitably, chip designers are following suit, not just to match the
chipmakers in their march to smaller feature sizes, but to polish their
own competitive edge with high-performance chip designs that are easy to
produce. They’re breaking out of a somewhat isolated mold, knowing
that shrinking design times and increasing layout complexity call for
new tools and expertise. Most acknowledge that the success of their
designs, and indeed, their future viability depends on quickly adopting
the tools and expertise that their chip making customers are using so
effectively.
The
Role of ICs in the Creation of a Connected World and the importance of
Product
Quality
Atiq
Raza
Chairman and CEO, Raza
Foundries Inc.
ISQED 2002, March 20, 2002
Human
Beings being social have had a need to communicate. The modem chapter in
enabling large-scale communication has been aided by intelligence in the
transport, distribution, protection, traffic management, decoding,
analyzing and displaying of communication content. The intelligence has
been embedded in an explosive confluence of Software, Systems and Integrated Circuits. This has resulted
in the most amazing transformation of the way we live our lives, work,
and engage in all other necessary and capricious activity. It has also
created a huge economic footprint on the Gross Domestic Product of the
United States of America. With a massive transformation that has
occurred in such a short time, this throbbing network across the planet
has to operate reliably because of the precious payload it carries.
Wireless
Systems-on-a-Chip Design
Bob
Brodersen
Dept. of EECS, University of California, Berkeley
ISQED 2002, March 20, 2002
There
is a fundamental shift that is occurring in the implementation of
wireless systems. Not only is the underlying technology shifting to
mainstream CMOS technology, but the applications and specifications of
the supported links is also rapidly evolving. The multiple inter-related technologies required
for implementation of such wireless systems requires a co-design
strategy in communication algorithms, digital architectures as well the
analog and digital circuits required for their implementation. Critical
to good design of these chips is the definition of energy and area
performance metrics that can facilitate the tradeoff of issues such as
the cost of providing flexibility or the amount of parallelism to
exploit. These design decisions can result in differences of orders of
magnitude in the metrics between what is possible in the technology and
what is often achieved if the costs are not fully understood. A design
infrastructure which supports architectures, which optimizes the
metrics, will be described for wireless systems that provides a fully
automated chip design flow design flow from a high level system
specification.
Microwave
III-V Semiconductors for Telecommunications and Prospective of the III-V Industry
Chan Shin Wu
President & CEO WIN
Semiconductors
ISQED 2002, March 20, 2002
The
Microwave m- v semiconductor IC technology (Primarily GaAs) has emerged
as a powerful, enabling, technology for the wireless and optical
communications in the past 5 years. It has been dominating, or making
substantial penetration into, the market for handset power amplifiers and switches, advanced
wireless LAN RF front-ends and various other key RF components for
broadband wireless, wireless infrastructure, satellite
telecommunications, high data rate fiber optical communications and
automotive radar applications. The Microwave III-V semiconductor IC
industry has grown dramatically in the past 2-3 years. It is worth
noting that the majority of the recently formed GaAs Fabs are located in
Taiwan. Their intent is to provide pure-play foundry services following
the silicon foundry business model developed by TSMC and UMC. In this
presentation, we will discuss the key components of III-V microwave
transistors (HBT, pHEMT and MESFET etc.) and their RFICs/MMICs, their
electrical performance, major applications, market status, trends and
opportunities. We will define the current status for the global m-v
semiconductors industry, the rapidly growing GaAs MMIC Fab industry in
Taiwan and its advantages for providing a one-stop, total solution for
the wireless and optical communication components customers.
Tomorrows
High-quality SoCs Require High-quality Embedded Memories Today
Ulf
Schlichtmann
Senior Director, Infineon
Technologies AG
ISQED 2002, March 20, 2002
Embedded
memories increasingly dominate SoC designs -whether chip area,
performance, power consumption, manufacturing yield or design time are
considered. ITRS data indicate that the embedded memory contents of ICs
may increase from 20% in 1999 to 90% at the SOnm node by the end of the
decade. Therefore, even more than today, the success of tomorrow's SoC
design will depend on the availability of high-quality embedded
memories. Advanced process technologies pose new challenges for meeting
these quality criteria. Some of the challenges are: providing flexible
redundancy solutions for embedded SRAMs; designing competitive memories
despite ever increasing leakage currents; reducing SRAM susceptibility
to soft-error rate (SER). These challenges are bringing about the need
for significant innovations in design of embedded memories, much more so
than in recent previous process generations. In the presentation, the
challenges will be outlined and solutions will be proposed. The focus of
the discussion will be on SRAM/ROM, but other technologies such as eDRAM
and "IT SRAM" will also be addressed.
Platform Leadership in the Ambient Intelligence Era
Bob
Payne
US
CTO and Senior Vice President/GM of System ASIC Technology, Philips
Semiconductors
ISQED 2003, March 25, 2003
Design
reuse has become essential to cope with the ever-increasing design complexity.
IP level reuse alone has proven insufficient. Platform based design allows the
validation of a robust combination of IP blocks and provides a reference HW and
SW baseline which can be supported with an integrated development environment.
Several years ago we transitioned into the streaming data era with most systems
serving as content generation appliances, content consumption appliances or
content distribution equipment. Now we have entered the age of ambient
intelligence where the streaming data is served up through wireless links. What
will platform leadership look like in this new era? How will the SoC
infrastructure change as we move to 90nm technology with more than 30M gate per
square centimeter integration capacity? How are usage patterns changing and what
represents the killer application that enhances the users quality of life by
enabling more advanced interaction with the ambient intelligence? What is it
going to take to make a step function improvement in system level design
productivity? What happens when power optimization becomes the dominant design
consideration? What about SoC affordability? What will the SoC design of the
future look like? These are just some of the thought provoking issues that will
be addressed in Bob Payne’s keynote.
Quality SoC Design and Implementation for Real
Manufacturability
Susumu
Kohyama
Corporate
Senior Vice President, Toshiba Corporation
ISQED 2003, March 25, 2003
Device
miniaturization near 100nm node and beyond together with extreme multi-level
interconnect started to create fundamental economical and engineering
challenges. Especially, past success model of “Layer Masters” confessed
difficulties to fill the gaps between each separated layers to complete
integrated results, for meeting performance and yield with a reasonable timing.
However, it is also obvious that classic IDM model proved to be so inefficient,
since inevitable separation and standardization of various aspects of design and
technology are not established adequately. Those issues are even more
significant when we discuss complex SoCs for 90nm and 65nm nodes, where design
and implementation commingle
in various different manners. A solution for these challenges is a new open idm
model where open collaboration and strong differentiator are essential.
This
presentation will discuss from a “SOC Centric Open IDM” perspective, the
whole flow of design and implementation for real manufacturability, where true
knowledge of integration and management skill function to enhance
differentiators on top of open platforms.
Quality Challenges of the Nanometer Design Realm
Ted Vucurevich
Senior
Vice President and Chief Technical Office, Cadence Design Systems, Inc.
ISQED 2003, March 25, 2003
It
is commonly agreed that sub-nanometer design is electronic design technology’s
next big challenge. With the economic stakes higher than ever, the vendors of
electronic design solutions must put themselves into their customers’ shoes
through comprehensive, high-quality programs. My understanding of the
differences designers face at geometries below 100 nanometers has led to my
discussion of some of the challenges the industry faces in the sub-nanometer
realm. This includes the domination of wires in digital design, which requires
the ability to design the best quality wires through continuous convergence, a
wire-centric methodology. In the nanometer world, the front-end and back-end
disappear, leaving the prototype as the chip. This includes detailed wiring, and
a new full-chip iteration every day. Most sub-nanometer ICs and SOCs will be
digital/mixed-signal. This leads to custom design issues, such as integrating
sensitive circuits with massive digital and mixed-signal design, productivity
and foundry interface. Nanometer soc verification includes digital, analog and
software, and a 70 percent silicon re-spin rate because of associated functional
errors. At sub-nanometer levels, design-in becomes a major bottleneck,
especially across a design chain, which can only be solved by
silicon-package-board co-design.
Addressing the IC Designer’s Needs: Integrated Design
Software for Faster, More Economical Chip Design
Rajeev Madhavan
Chairman &
CEO, Magma Design Automation
ISQED 2003, March 26, 2003
Electronic
design automation continues to attract a great deal of investment from the
venture community, fostering the creation of startup companies focused on
developing unique point-tool solutions. While many innovative new technologies
come from this, industry must consider the increasingly critical need of IC
designers and manufacturers: integrated design flows that enable the design and
production of chips with fewer resources and in less time, without compromising
the quality of results. Increasingly evident is the advantage of integrated
design and the economies it brings while delivering the same quality of results
as point-tool-based approaches. The future of EDA depends on the
industry’s ability to deliver solutions that enable the IC industry’s
integration of electronic design tools and processes as it relies on EDA to
provide the means for producing the next generation of semiconductor products.
Closing the Gap Between ASIC and Full Custom: A Path to
Quality Design
Michael
Reinhardt
President &
CEO, RubiCad Corporation
ISQED 2003, March 26, 2003
Although
process technology has shrunk down to nanometer features over the last decade,
the gap between ASIC design and full-custom ic design has widened. This gap
includes significant differences in performance, price, and profit between the
two design styles. It is also revealed by huge differences in quality between
the two styles in speed, power distribution and consumption, yield, and
reliability, in some cases as much as an order of magnitude. To fully utilize
the latest process technologies, a full-custom design approach with the
productivity of an ASIC flow is necessary.
A VLSI System Perspective for Microprocessors
Beyond 90nm
Shekhar
Borkar
Fellow
& Director of Circuit Research lab, Intel Corporation
ISQED 2003, March 26, 2003
Microprocessor
performance increased by five orders of magnitude in the last three decades.
This was made possible by continued technology scaling, improving transistor
performance to increase frequency, increasing integration capacity to realize
complex architectures, and reducing energy consumed per logic operation to keep
power dissipation within limit. The technology treadmill will continue to
fulfill the microprocessor performance demand; however, with some adverse
effects posing barriers—limited by power delivery and dissipation—and not by
manufacturing or cost. Therefore, performance at any cost will not be an option;
significant improvements in efficiency of transistor utilization will be
necessary. This talk will discuss potential solutions in all disciplines, such
as micro-architecture, circuits, design technologies & methodologies,
thermals, and power delivery, to overcome these barriers for microprocessors
beyond 90nm.
Simplify: Enable Quality, Enable Innovation
John
Chilton
Sr. VP and General Manager,
Synopsys, Inc.
ISQED 2004, March 23,
2004
As
the old sales adage goes, “Nothing happens until somebody sells something.”
For the semiconductor-based electronics industry, the never-ending challenge is
to find and sell the next IC-based new “something” (or “somethings”)
that consumers just can’t live without. It’s an immense and extremely
expensive undertaking to find/create/deliver a killer app, requiring a
single-minded, undistracted business focus and an immense amount of creative
design innovation. Fortunately, there is a wealth of business-savvy, creative
systems companies able to meet that challenge, as long as they are free to
concentrate on what drives their core competency: designing and selling exciting
new business systems and consumer devices. What they need from their chip
manufacturers is an agreement on specs, models, pricing, and delivery. Simple.
Fortunately, there are semiconductor firms up to the challenge, as long as they
are free to exercise their core mission: designing and selling faster and
slicker chips, often now with software and boards attached. They need to focus
on taking their customer’s performance specifications and turning out a system
on a chip that does exactly those things, on time and on budget. What they need
from their EDA vendors are tightly integrated design tools that allow them to
meet their goals of performance, price, and predictability. Simple.
Unfortunately, these industries don’t reflect this simplified, rosy picture…
yet. The hard reality is, however, that they do have to get there, and soon, or
live with dwindling prospects for the future. This presentation will discuss
strategies for simplifying the semiconductor value chain, thereby enabling each
segment to focus on doing well what it does best, for the sake of the future of
the entire electronics industry.
Design for Manufacturing? Design for Yield!!!
Marc
Levitt
Vice
President and General Manager
Cadence
Design Systems, Inc.
ISQED 2004, March 23,
2004
Today’s
nanometer-scale designs are two orders-of-magnitude more complex than designs
were in the early 1990s and are commonly manufactured with processes at or below
the 130nm feature size. This has brought about a fundamental change in the way
design teams must approach the release for their design data to their
manufacturing partners. In the past, once a design was taped out and proven to
be functional, the responsibility for ramping yield and enhancing the
profitability of a design was primarily the responsibility of the manufacturing
partner. This is no longer possible at 130nm and below. Once a manufacturing
process has stabilized, direct action must be taken by each and every design
team to "tune" their design for yield. Design-specific yield
enhancement is the new frontier in EDA and while it includes the traditional
Design for Manufacturing (DFM) technologies, it also covers much more. Failure
to consider yield-degrading effects in IR drop, signal integrity, electro
migration, and process variation will result is severe downstream problems in
timing closure, functional errors during system bring-up, and the inability to
achieve silicon yield and quality targets.
Nanotechnology-Nanoscale Molecular Memory
Shih-Yuan
(SY) Wang
Senior
Scientist Quantum Science Research
Hewlett
Packard Laboratories
ISQED 2004, March 23,
2004
An overview of nanotechnology research at HP Labs/ Quantum Science Research
will be given with focus on nanoscale molecular memories. Densities of 100 Gb/cm2
are within reach. QSR aim is to break away from the current “scaling” down
approach and look for and/or invent innovative approaches that have the
potential for high volume manufacturability to break through the ITRS Red Brick
Wall and push the limit of the technology. Nanofabrication challenges and
possible applications will also be discussed.
Digitally Named World: Challenges for New Social
Infrastructures
Hiroto
Yasuura
System Research Center
Kyushu University, Fukuoka, Japan
ISQED 2004, March 24,
2004
In
the last three decades of the 20th century, many information and communication
technologies have been developed and also introduced in social infrastructures,
which are supporting our daily lives. Since the information technologies have
progressed very rapidly, the basic structure of each social infrastructure,
which was mostly designed in the 19th or the beginning of 20th centuries with
few possibility of information technology, should be redesigned with an
assumption of the existence of the advanced information technologies. Based on
the high-performance SoCs (System-on-a-Chips) connected by wide-band networks,
we can design next generation of social systems, which are directly related with
quality of our society including individual rights and national security. In
this talk, two social infrastructure information technologies are introduced.
Personal Identifier (PID) system is an infrastructure for bidirectional mutual
authentication, which will be used for electric commerce and governmental
services. An RF-ID tag system is also important technology to implement
efficient management of products and economic activities. Using PID and RF-ID
tags, we can bridge a gap between the real world and the virtual one on
computers automatically. We call the society, in which all persons and goods
have their own digital names (identifiers) and are recognizable both in the real
and virtual world, Digitally Named World. The systems require advanced
technologies of SoC, networking, security and software. Here, technical
challenges and social requirements for the new technologies are discussed. Some
people are afraid of the infringement of their privacy in the digitally named
world. Our discussions also include the technology to protect privacy and
individual rights as well as efficiency and stability of our society.
Designing High Quality, Scaleable SoC’s with
Heterogeneous Components
Pierre
G. Paulin
Director, SoC Platform Automation
Central R&D, STMicroelectronics,
Ottawa, Canada
ISQED 2004, March 24,
2004
Today’s
SoC’s combine an increasingly wide range of heterogenous processing elements,
consisting of general purpose RISC’s, DSP’s, application-specific
processors, and fixed or configurable hardware. Five to ten processors on an SoC
is now common. A bottom-up assembly of these heterogeneous components using an
ad-hoc interconnect topology, different instruction sets and embedded S/W
development tools leads to unmanageable complexity and low quality. This talk
will present an approach to effectively integrate heterogenous parallel
components – H/W or S/W – into a homogeneous programming environment. This
leads to higher quality designs through encapsulation and abstraction. This
approach, supported by ST’s MultiFlex multi-processing SoC tools, allows for
the combination of a range of heterogeneous processing elements, supported by
high-level programming models. Two programming models are supported: a
distributed system object component (DSOC) message passing model, and a
symmetrical multi-processing (SMP) model using shared memory. We present the
results of mapping an Internet traffic management application, running at
2.5Gb/s. We demonstrate the combined use of the MultiFlex multi-processor
compilation tools, supported by high-speed hardware-assisted messaging,
context-switching and dynamic task allocation in the StepNP platform.
Performance Limitations of Devices and Interconnects
and Possible Alternatives for Nanoelectronics
Krishna
Saraswat
Rickey/Nielsen Professor of Engineering
Stanford University
ISQED 2004, March 24,
2004
For
over three decades, there has been a quadrupling of transistor density and a
doubling of electrical performance every 2 to 3 years. Si transistor technology,
in particular CMOS has played a pivotal role in this. It is believed that
continued scaling will take the industry down to the 35-nm technology node, at
the limit of the ”long-term” range of the International Technology Roadmap
for Semiconductors (ITRS). However, it is also well accepted that this long-term
range of the 70-nm to 35-nm nodes remains solidly in the “no-known solution”
category. The difficulty in scaling the conventional MOSFET makes it prudent to
search for alternative device structures. This will require new structural,
material and fabrication technology solutions that are generally compatible with
current and forecasted installed Semiconductor Manufacturing. In addition, new
and revolutionary device concepts need to be discovered and evolved. These can
be split into two categories: one is the continued used of silicon FET-type
devices but with additional materials, e.g., Ge and innovative structural
aspects that deviate from the classical planar/bulk MOSFET, e.g., double gate
MOSFET. The second category is a set of potentially entirely different
information processing and transmission devices from the transistor as we know
it, e.g. silicon-based quantum-effect devices, nano-tube electronics and
molecular and organic semiconductor electronics. Continuous scaling of VLSI
circuits can pose significant problems for interconnects, especially for those
responsible for long distance communication on a high performance chip. Our
modeling predicts that the situation is worse than anticipated in the ITRS,
which assumes that the resistivity of copper will not change appreciably with
scaling in the future. We show that resistance of interconnect wires in light of
scaling induced increase in electron surface scattering, fractional cross
section area occupied by the high resistivity barrier and realistic interconnect
operation temperature will lead to a significant rise in the effective
resistivity of Cu. As a result both power and delay of these interconnects is
likely to rise significantly in the future. In the light of various metal
interconnect limitations, alternate solutions need to be pursued. We focus on
two such solutions, optical interconnects and three-dimensional (3-D) ICs with
multiplicative Si layers.
Enabling True Design for Manufacturability
John Kibarian
President
& CEO, PDF Solutions
ISQED 2005, March 22,
2005
Without any doubt, Design For
Manufacturability has been the hottest buzzword for the last couple of
years. This is quite justifiable by the enormous challenges in nanometer
technology nodes and ever increasing design-process interactions. As a
result, virtually all EDA companies have focused on providing the
"DFM Solutions". Since
the concept of DFM covers an extremely broad spectrum of tasks from the
system level all the way to the manufacturing process, many of these DFM
solutions are just the re-labeled design verification tasks.
Recent progress and remaining challenges in pattern transfer
technologies for advanced chip designs
Ashok K. Sinha
Sr. VP & GM
Applied Materials,
Inc
ISQED 2005, March 22,
2005
Even as the Moore's law continues to drive "tiny
technologies" through relentless scaling, the main technology
driver for semiconductor chips has evolved from DRAMs to Microprocessors
to FPGAs. The underlying metrics have evolved from bits per chip and
cost per bit for computers to functions per chip and cost per function
for consumer products. This talk will review the remarkable progress
that has been made in enabling pattern transfer technologies, including
mask design, lithography enhancements and precision etching on the new
300mm wafers for an increasingly wide variety of new materials. However,
there is a cost associated with all this and the cost-benefit tradeoffs
will almost certainly drive new inflections in the entire food chain,
which I will try to identify.
Shifting Perspectives on DFM
Janusz
Rajski
Chief
Scientist, Design Verification and Test Division
Mentor
Graphics
ISQED 2005, March 22,
2005
Nanometer technology
has ushered in new and significant yield and manufacturing
considerations and constraints. The lack of major increase in yield
improvement between the 350nm and 180nm nodes suggests that the yield
loss mechanisms are not only increasing in numbers, magnitude, and
complexity at each successive generation, but they are increasing at a
rate fast enough to largely offset ‘cosmetic’ improvements in tools
and methodologies. If EDA tools are to
assist the semiconductor industry at the 90nm and 65nm nodes, there must
be profound changes to existing tools, and the introduction of new
technologies that allow designers to consider and optimize for
manufacturing at each stage of the design, verification, tapeout and
test process.
Collaboration, Quality and Value in the Design Chain
David
Courtright
Vice
President and Chief Technology Officer, Cadence Design Systems
ISQED 2005, March 23,
2005
Meeting the challenges of product
development cycles and managing the complexity of increased
semiconductor functionality has created a demand for a virtual
reaggregation of the silicon design chain.
These challenges continue to multiply with the concurrent move to
smaller geometries.
This presentation, will address the
challenges by calling for an industry commitment to collaborate across
the design chain. It is
shown how collaboration is necessary for companies to meet
time-to-market demands and manage the increasing complexity in chip
design, while preserving the intellectual property of each member of the
design chain. The speaker will also discuss the need for developing
higher quality EDA tools as a means to the end of developing the next
generation of electronics products.
IP Quality: A New Model that Faces Methodology and Management
Challenges
Kurt A. Wolf
Director,
Library Management Division
TSMC
ISQED 2005, March 23,
2005
The promised value and productivity from
re-aggregating the IC design chain isn’t always delivered, in part
because of isolated IP product development/quality related practices,
and in part because of an inability, from a design management
perspective, to see “big picture” issues in the IP marketplace.
However, these challenges are not insurmountable.
The concern over IP quality has
rightfully grown over the past years as the future growth of the IC
industry depends on two factors; a) achieving higher levels of design
productivity and b) shifting internal resources towards creating and
delivering value-added user benefits that stimulate increased
end-product consumption. While
the second factor is not discussed in this presentation, there’s a
presumption that higher IP quality and productivity enables a shift of
resources to more applications-oriented design.
A pre-requisite to achieving the
productivity gains is substantial improvements in the level of IP
quality, coupled with increased forethought during product development.
This presentation describes a methodology to evaluate IP for SOC
integration. The focus is on
development & quality verification practices that also account for
the issues of IP integration.
Additionally,
the long-term growth of the semiconductor industry may be limited by the
lack of value placed on collaboration, support, quality verification,
and due diligence between SOC design teams and their IP partners.
This presentation also describes
improvements in the Hard IP business relationship between these groups
that enable dramatic growth through slight changes in communications
models.
By developing reasonable expectations and
focusing on open discussion between each group, perspective begins to
shift. The true value of the
design team and IP partnership is a function of successful
collaborations – not when the user squeezes the last drop out of NRE,
royalty, per-use, or other financing models.
And the value-add of the partnership is realized when that
collaboration includes additional real, shared incentives that more
fully value the IP industry, rather than focus on purely lowest cost.
SoC Engineering Trends as Impacted by New Applications and System
Level Requirements
Bernard
Candaele
Department Head, SoC, IC & EDA
Thales, Paris Colombes, France
ISQED 2005, March 23,
2005
The SoC
increasing integration scale as well as the system and customer
requirements are important factors for a complete revisit of the
development models for electronic products. New customer models ask for
software driven electronics. Software engineering is moving to a
component-based and MDA development approach to be applied to embedded
applications. Hardware engineering is moving to SSDI System Level
Development and Reuse methodologies. The 2 approaches have now to be
further developed and combined for next generations SoC’s to get high
quality and adaptable designs at a reasonable development cost.
New application-level quality standards have also to be part of
the complete development flow.
It is
demonstrated through several examples these new methodologies: system
engineering methodology on software radios (UML, PIM Platform
Independent Model and PSM Platform Specific Model) and its current
extension to the hardware parts (SCA, OCP potential extensions), system
engineering in line with the C |
