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Session 1C

Tuesday 3/21/00

1:25pm - 3:10pm

 

Emerging Process and Device Technologies

 

Co-Chairs: David Overhauser, Simplex Solutions, Chune-Sin Yeh, BTA

 

1:25pm

Introduction

1:30pm

1C.1 Overview of SiGe: Technology, Modeling and Application (Invited)

Peter Yuan, University of Central Florida, Orlando, FL

1:55pm

1C.2 GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design

L. Wu*, J. Fang* , H. Yonezawa** , H. Yan* , Y. Kawakami** , N. Iwanishi**, P. Chen* , A. Chen* , N. Koike** , Y. Okamoto** , C. Yeh* , Z. Liu*, * BTA Technology, San Jose, CA, **Matsushita Electric Industrial, Co., Kyoto, Japan

2:20pm

1C.3 An Efficient Rule Based Opc Approach Using A DRC Tool

For 0.18um ASIC

Ji-Soong Park, Chul-Hong Park, Sang-Uhk Rhie, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong, Hyung-Woo Kim, and Sun-Il Yoo, Samsung Electronics, Korea

2:45pm

1C.4 Three Dimensional Analysis of Thermal Degradation Effects in FDSOI MOSFET’s

Kwan-Do Kim, Young-Kwan Park, Jun-Ha Lee, Jeong-Taek Kong , Hee-Sung Kang, and Young-Wug Kim, Samsung Electronics, Korea


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International Symposium on Quality of Electronic Design
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Revised: May 13, 2001 .