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Workshop I

RF IC Design for Wireless Communication

Organizer & Moderator:

Antonio Nunez, University of Las Palmas


The boom of wireless and mobile communications leads to an increasing request for low cost and low power mixed mode integrated circuits. Maturity of  silicon-based technology and recent progress of MOSFET’s microwave  performance, explain the silicon success in many circuits as compared to III-V technologies.  This is leading to highly integrated systems on a chip. Driving applications range from cell phones to Bluetooth and other IEEE 802.11x Wireless LAN standards. Analysts have predicted almost 800 million worldwide wireless data users by 2004. This demand is driving manufacturers, celco&telco operators, and companies to get ready for a flood of new mobile devices -on the streets and in the enterprises-, supporting three distinct solutions: low-speed wireless data only; voice plus web access; and high-speed wireless LAN access. Design engineers need to cope with this variety of standards, while keeping the low-power low-cost design targets that the industry is set to meet. Silicon substrates are not inherently well suited for RF IC design in many key aspects for both passive and active components. This fact poses plenty of design challenges where the creativity, experience, training and practical skills of design engineers are most needed. EDA tool development needs also further advance since the industry requires an increase in design productivity, hard to achieve in analog, mixed signal, and RF integrated circuits. In spite of all these challenges, many success stories in component design for RFICs are shown in the workshop, covering designs from PLL, VCO, PA, LNA and transceivers to filters and high Q inductors integrated on Silicon. In addition, Silicon-on-Insulator-based MOSFETs are very promising devices for multigigahertz applications. Especially low microwave noise at low drain voltage bias condition is one of the very interesting high frequency  characteristics of such devices. Moreover, due to the reduction of channel dimension and the improvement of electrode processes (salicide, metal  T-gate processes), very low noise integrated circuits operating beyond 10  GHz and more can be realized. Details of  state-of-the-art high frequency performance of sub-250 nm gate  length FD SOI MOSFETs will also be given in the workshop as well as demonstration of the capabilities of integrating  high quality passive components on SOI wafers. Finally key practical issues for on- and off- wafer RFIC test and measurement techniques will be given in the last part of this one day workshop organized with the aim of providing in depth, practical and proven design solutions for practicing design professionals.

Workshop Schedule:

8:30-10:15 Session I-1

CMOS Multistandard Transceivers for Wireless Communication

Mohammed Ismail, Ohio-State University, OH

The Challenge of Passive Component Design on Silicon

Antonio Hernandez, University of Las Palmas, Spain

10:15-10:30     coffee break


10:30-12:15 Session II-2

Automatic Integrated Inductor Design

José R. Sendra, University of Las Palmas, Spain

Key Issues in Integrated PLL-VCO Design for Wireless Standards

Javier  Hernandez, INCIDE, San Sebastian, Spain


12:15-1:15pm    lunch

1:15-3:00pm Session I-3

Design Practice for CMOS RF Circuits at 5GHz and Beyond?

Tom Lee, Stanford University, CA


SOI for RFIC Design

Jean-Pierre Raskin, UCL, Louvain-la-Neuve, Belgium


3:00-3:15pm     coffee break


3:15-5:00pm Session I-4

Power Amplifier Design

Hamid Rategh, Tavanza, Sunny Vale, CA

On Wafer RFIC Measurement Techniques

Tariq  Alan/Antony Lord, Cascade Microtech, Beaverton, OR

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International Symposium on Quality of Electronic Design
Copyright © 1998-2002 ISQED. All rights reserved.
Revised: February 21, 2002.